Serial, Networking & Storage

MACsec (IEEE 802.1AE) Frame Authentication/Encryption Endpoint

Single-link MACsec endpoint — GCM-AES-128 AND GCM-AES-256 per SA, reuses the catalog’s own ASIL-B AES/GCM engine.

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ASIL-B

target

97.70%

SPFM

89.70%

LFM

PASS

FMEDA

217K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

Single-link MACsec endpoint — GCM-AES-128 AND GCM-AES-256 per SA, reuses the catalog’s own ASIL-B AES/GCM engine. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable MACsec (IEEE 802.1AE) frame authentication/encryption endpoint soft-IP, supporting both GCM-AES-128 and GCM-AES-256 independently per Security Association — a standalone digital IP sitting between a MAC and a PHY (conceptually), matching this catalog’s “digital-only, connects to an external MAC/PHY” convention already used for eth_pfc/dp_link.

Key Features

Four independent byte-stream ports (rx_in/rx_out, tx_in/tx_out), store-and-forward buffered, genuine valid/ready backpressure
GCM-AES-128 AND GCM-AES-256, independently selectable per SA slot (SA\_CTRL.KEY256) — mixed-width links supported
Reuses the shipped ASIL-B aes engine’s own hardware GCM sequencer via an internal microsequencer — no AES/GHASH re-implemented
2 CSR-configurable SA slots per direction — RX accepts either configured SA, TX has an explicit active-SA-select trigger
32-bit PN with CSR-configurable replay-window protection (RX) and PN-exhaustion refusal, never silent wrap/reuse (TX)
Diverse-DMR FSM lockstep spanning the RX FSM, TX FSM, AND the AES-microsequencer driver FSM (err_code 9)
Config + datapath register parity, plus DISTINCT auth-failure / replay-rejection / malformed-SecTAG faults, individually visible in STATUS

Standards & Compliance

IEEE 802.1AE MACsec (public shape only — clean-room reduced-scope approximation, not a verified implementation of the licensed specification)

Functional Safety

ASIL-B (SEooC) · SPFM 97.70% · LFM 89.70% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=RX_EN [1]=TX_EN [2]=TX_SA_SEL (select active TX SA slot 0/1) [3]=RX_DROP_ON_FAIL (0=release plaintext anyw…
`0x04`	STATUS	RO/W1C [0]=RX_BUSY (RO) [1]=TX_BUSY (RO) [2]=RX_DONE (W1C) [3]=TX_DONE (W1C) [4]=RX_AUTH_FAIL (W1C) [5]=RX_REPLAY_FAI…
`0x08`	IER	RW [7:2] = per-STATUS-bit interrupt-enable mask, aligned 1:1 to STATUS[7:2] (bits [1:0] reserved; no irq pin in v…
`0x0C`	REPLAY_WINDOW	RW [15:0] = RX replay-window size (a PN more than this far behind the highest-seen PN for the matching SA is rejected…

Getting Started

// Minimal instantiation
macsec_node #(
 .ADDR_W(6)
) u_macsec_node (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in MACsec (IEEE 802.1AE) Frame Authentication/Encryption Endpoint?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space