Motor, Power & Sensor Control

Motor-Control PWM (Dead-Time / Trip-Safe)

Center-aligned 3-phase complementary PWM with hardware dead-time and a structural trip safe-state for BLDC/PMSM inverters, ASIL-D SEooC.

Request this IP →Browse the catalog

ASIL-D

target

100.00%

SPFM

100.00%

LFM

PASS

FMEDA

2.3K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

Center-aligned 3-phase complementary PWM with hardware dead-time and a structural trip safe-state for BLDC/PMSM inverters, ASIL-D SEooC. It is delivered as a licensable soft-IP block engineered as an ASIL-D Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable motor-control PWM generator delivered as synthesizable SystemVerilog soft-IP. It produces N-phase (default 3-phase) complementary high-side/low-side gate signals with a center-aligned (up/down) carrier, programmable dead-time insertion to prevent shoot-through, a hardware trip input for immediate safe-state forcing on fault, and an ADC start-of-conversion sync pulse.

Key Features

Center-aligned (up/down) carrier with per-phase duty compare (PERIOD, DUTY0_DUTY2); NPH complementary output pairs (default 3) with per-phase enable (CHEN)
Hardware dead-time insertion (DEADTIME, or asymmetric per-phase DT_RISE/DT_FALL) blanks both gates of a phase around every HS polarity edge — shoot-through prevented structurally
Async hardware trip input (trip_n) forces an immediate safe state (all-off, or low-side-on for dynamic braking under CTRL.BRAKE) via logic parallel to the digital control path
TMR-masked carrier (3 rails, 2-of-3 vote): a single-rail SEU is masked and switching continues correctly while err_code 9 flags the latent fault, with a diverse antivalent comparator shadow retained for genuine redundancy
Independent-DMR coverage on dead-time counters, carrier direction, HS edge history, and the trip latch itself (err_code 9) — closes the residual a stuck safe-state latch would otherwise leave silent
Even-parity protection on every config register (err_code 1); ADC start-of-conversion sync pulse (adc_soc) aligned to the carrier valley/peak for clean current-sense sampling
ASIL-D SEooC: SPFM 100.00%, LFM 100.00%, PMHF 1.27×10⁻¹⁰/h, with fault-injection-measured 100% SPF DC on the config, comparator/dead-time, trip, and reporting regions

Standards & Compliance

AMBA APB4 (ARM IHI 0024); IEC 61800-5-2 (electrical motor drive functional safety); ISO 26262 ASIL-D SEooC (SPFM 100.00%, LFM 100.00%, PMHF 1.27×10⁻¹⁰/h)

Functional Safety

ASIL-D (SEooC) · SPFM 100.00% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=BRAKE (trip -> low-side on; else all off)
`0x04`	STATUS	[0]=TRIPPED [1]=DIR (carrier counting up) [2]=RUNNING (RO)
`0x08`	PERIOD	carrier top (center-aligned counts 0..PERIOD..0)
`0x0C`	DEADTIME	dead-time in clocks (symmetric fallback: used for both rise/fall if DT_RISE==0&&DT_FALL==0)

Getting Started

// Minimal instantiation
mc_pwm #(
 .ADDR_W(6)
) u_mc_pwm (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in motor drives, power conversion, and sensor front-ends in automotive and industrial systems.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Motor-Control PWM (Dead-Time / Trip-Safe)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space