Cryptography & Data Integrity

ML-DSA Infinity-Norm Check (mldsa\_norm)

mldsanorm is the rejection gate of post-quantum ML-DSA (Dilithium, FIPS 204) signing — the fifth building block of the ML-DSA line.

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ASIL-B

target

92.12%

SPFM

94.97%

LFM

PASS

FMEDA

7.0K

gates

1.0.0

version

The deliverable

What you’re licensing

mldsanorm is the rejection gate of post-quantum ML-DSA (Dilithium, FIPS 204) signing — the fifth building block of the ML-DSA line. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

mldsa_norm is the rejection gate of post-quantum ML-DSA (Dilithium, FIPS 204) signing — the fifth building block of the ML-DSA line. It implements poly_chknorm: given a polynomial of centred coefficients and a runtime bound B, it decides whether any coefficient’s magnitude reaches B, and if so rejects the whole polynomial.

Key Features

Constant-time infinity-norm check (poly_chknorm): |coeff| formed branchlessly via the sign-mask identity a − (sign & 2a), bit-exact with the pq-crystals dilithium reference across pass/mid/edge/guard-bound directed vectors
One coefficient per cycle over a 256-coefficient polynomial (centred representatives, q=8380417); reports norm_fail plus the violation count (viol_cnt, 0..256) and the index of the first violator (first_idx)
Runtime bound B (not hardwired): the same core serves all three ML-DSA Sign rejection gates — ‖z‖∞<γ1−β, ‖r0‖∞<γ2−β, ‖c·t0‖∞<γ2 — by reloading B and the coefficients between checks
Hardware bound guard: B > (q−1)/8, where the centred-abs identity is no longer sound, is rejected outright (norm_fail=1) at start rather than silently mis-evaluated
Bare compute-core handshake (wr_en/wr_addr/wr_data, bound/start, busy/done) — no APB/AXI aperture, drops straight behind a CPU or Sign-sequencer FSM with no bus-protocol overhead
ASIL-B safety: coefficient-scan control-FSM duplicate-DMR lockstep (err_code 9) + op-sequence parity (err_code 1) into a shared safety_monitor; coefficient-RAM SECDED is a documented Assumption of Use (err_code 2 via ecc_sram)
SPFM 92.12%, LFM 94.97%, PMHF 1.04×10⁻⁸ /h against the ASIL-B target — PASS with margin on all three metrics (informational-preview FMEDA)

Standards & Compliance

FIPS 204 (ML-DSA/Dilithium poly_chknorm); ISO 26262 ASIL-B SEooC (SPFM 92.12%, LFM 94.97%, PMHF 1.04×10⁻⁸ /h)

Functional Safety

ASIL-B (SEooC) · SPFM 92.12% · LFM 94.97% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
mldsa_norm #(
  .ADDR_W(6)
) u_mldsa_norm (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ML-DSA Infinity-Norm Check (mldsa\_norm)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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