Cryptography & Data Integrity

ML-DSA / Dilithium Coefficient (De)Serializer

mldsapack is the byte-packing glue of post-quantum ML-DSA (Dilithium, FIPS 204) signatures — the fourth building block of the ML-DSA line,

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ASIL-B

target

91.87%

SPFM

94.66%

LFM

PASS

FMEDA

12.0K

gates

1.0.0

version

The deliverable

What you’re licensing

mldsapack is the byte-packing glue of post-quantum ML-DSA (Dilithium, FIPS 204) signatures — the fourth building block of the ML-DSA line, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

mldsa_pack is the byte-packing glue of post-quantum ML-DSA (Dilithium, FIPS 204) signatures — the fourth building block of the ML-DSA line, and the direct counterpart of ML-KEM’s mlkem_pack.

Key Features

One generic bit-accumulator engine for all five Dilithium poly formats via runtime (bits, off, sub): t1 (10b, direct, public-key high), t0 (13b, 2¹²−coeff, secret-key low), s1/s2 (4b, η−coeff), z (20b, γ1−coeff, signature response), w1 (4b, direct, commitment high) — bit-exact with the pq-crystals polyt1/t0/eta/z/w1 pack + unpack
Bare host-load compute-core interface: wr_en/wr_sel/wr_addr/wr_data load the 256×32 coefficient RAM or the 704×8 byte RAM; op/start dispatch PACK or UNPACK; rd_addr/rd_coeff/rd_byte read back — no bus wrapper, writes gated to the FSM’s idle state
Format config (bits/off/sub) is sampled live every cycle rather than latched at start, so the integrator must hold it fixed for the whole PACK/UNPACK burst — a documented correct-deployment obligation, not a hardware interlock
Plugs directly into the FIPS 204 KeyGen/Sign/Verify pipeline: PACK t1/t0/s1/s2 for key generation, UNPACK the secret key plus PACK w1/z for signing, UNPACK the public key and signature plus PACK the recomputed w1′ for verification
Control-FSM duplicate-DMR shadow reports any divergence as err_code 9
Op-sequence parity check reports a corrupted operation count as err_code 1
Coefficient/byte-RAM SECDED is a documented Assumption of Use (wrap in ecc_sram → err_code 2) to keep the credited ASIL-B SPFM

Standards & Compliance

FIPS 204 (ML-DSA/Dilithium byte-packing: t1/t0/eta/z/w1); pq-crystals dilithium reference-algorithm bit-exactness; ISO 26262 ASIL-B SEooC (SPFM 91.87%, LFM 94.66%, PMHF 1.84×10⁻⁸/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.87% · LFM 94.66% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
mldsa_pack #(
  .ADDR_W(6)
) u_mldsa_pack (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ML-DSA / Dilithium Coefficient (De)Serializer?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

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Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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