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AI Inference & Acceleration

NPU Activation

npuact is a self-checking transformer post-GEMM activation / normalization unit,

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ASIL-B
target
96.40%
SPFM
91.60%
LFM
PASS
FMEDA
2.2K
gates
1.0.0
version
The deliverable

What you’re licensing

npuact is a self-checking transformer post-GEMM activation / normalization unit, It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

npu_act is a self-checking transformer post-GEMM activation / normalization unit, delivered as synthesizable SystemVerilog soft-IP with an AXI4-Stream data path, an APB4-lite control interface, and built-in ISO 26262 (ASIL-B) safety instrumentation.

Key Features

Standards & Compliance

ISO 26262 (ASIL-B), pairs with ai_mac / tensor_dma (AI subsystem)

Functional Safety

ASIL-B (SEooC) · SPFM 96.40% · LFM 91.60% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

OffsetRegisterDescription
0x00CTRLRW [2:0]=MODE, [3]=EN
0x04ROWLENRW [15:0] elements per row (1..MAX_ROW)
0x08IN_SCALERW [31:0] Q16.16 input scale (element_real = int16 * IN_SCALE)
0x0CEPSRW [31:0] Q16.16 variance/denominator epsilon (LayerNorm / RMSNorm)
0x10ABFT_TOLRW [31:0] Q16.16 invariant tolerance (softmax row-sum / LN moments)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
npu_act #(
  .ADDR_W(6)
) u_npu_act (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months
The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.
One vendor, one safety story
Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.
Verified, not vapor
The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in NPU Activation?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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