System, Safety & Compute

pll_guard — PLL / Clock-Integrity Safety Supervisor

Digital safety supervisor that proves a vendor analog PLL’s output clock is locked, in-band, and stable…

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ASIL-D

target

99.66%

SPFM

100.00%

LFM

PASS

FMEDA

2.0K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

pll_guard — PLL / Clock-Integrity Safety Supervisor routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Digital safety supervisor that proves a vendor analog PLL’s output clock is locked, in-band, and stable… It is delivered as a licensable soft-IP block engineered as an ASIL-D Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

pll_guard is the clock-integrity safety supervisor for an SoC’s main PLL, delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-D) safety instrumentation.

Key Features

Lock supervision: P1 lock-loss (pll_lock_i deasserts after lock) and P2 lock-acquire watchdog (LOCK_TO) both drive safe_state_o with err_code 4
P3 lock-bounce (BOUNCE_N accumulated lock-drops) and P4 frequency-in-band (Gray-CDC tick count vs F_MIN/F_MAX) drive safe_state_o with err_code 3
P5 lock∧frequency cross-check — clock-good = lock AND in-band AND stable — catches “locked-but-wrong” (false/harmonic lock, reference drift) that a lock pin alone cannot
P6 glitch-free safe-clock switchover FSM (PLL→settle→SAFE) hands clk_sel_o to the fallback with no runt pulse, held sticky until a supervised err_clear
P8 DMR-duplicated detection state and switch FSM (KEEP_ATTR shadows): a single upset diverges the shadow and fail-safe-asserts safe_state_o plus err_code 9, so the guard cannot be silently blinded
P7 config-register parity (CTRL/LOCK_TO/F_MIN/F_MAX/WINDOW/BOUNCE_N) reports err_code 1 for an SEU in the threshold set
APB4-lite register map (paddr[4:2]): CTRL 0x00, LOCK_TO 0x04, F_MIN 0x08, F_MAX 0x0C, WINDOW 0x10, BOUNCE_N 0x14, STATUS 0x18, TELEM 0x1C; verified by 45 directed checks covering P1-P8

Standards & Compliance

ISO 26262 ASIL-D SEooC (SPFM 99.66%, LFM 100.00%, PMHF 1.41×10⁻¹⁰/h); APB4-lite config/status interface

Functional Safety

ASIL-D (SEooC) · SPFM 99.66% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN, [1]=FREQ_CHK, [2]=BOUNCE_CHK, [3]=ACQ_CHK
`0x04`	LOCK_TO	RW [31:0] lock-acquire watchdog timeout (clk cycles from enable; 0=off)
`0x08`	F_MIN	RW [15:0] lower band: min pll_clk_i ticks per window
`0x0C`	F_MAX	RW [15:0] upper band: max pll_clk_i ticks per window
`0x10`	WINDOW	RW [15:0] frequency-measure window length (clk cycles)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
pll_guard #(
 .ADDR_W(6)
) u_pll_guard (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in pll_guard — PLL / Clock-Integrity Safety Supervisor?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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