Serial, Networking & Storage

Quad-SPI Flash Controller

X1/X2/X4 QSPI NOR-flash controller sized for the boot/config-storage path — ECC-protected FIFOs, ASIL-B SEooC.

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ASIL-B

target

95.10%

SPFM

90.00%

LFM

PASS

FMEDA

1.5K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Quad-SPI Flash Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

X1/X2/X4 QSPI NOR-flash controller sized for the boot/config-storage path — ECC-protected FIFOs, ASIL-B SEooC. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable Quad-SPI (QSPI) NOR-flash controller delivered as synthesizable SystemVerilog soft-IP, sized for the boot and configuration-storage path of a safety-critical SoC.

Key Features

Single / dual / quad (X1/X2/X4) I/O modes selectable at runtime via CR.MODE, sharing one 4-bit tri-stated qspi_io pad bus
Standard NOR-flash command/address/dummy/data phase protocol with software-configurable dummy-cycle count and all four SPI clock modes (CPOL/CPHA)
TX / RX SECDED byte-wide FIFOs (fifo_ecc): single-bit upsets corrected in-line, double-bit errors latched as err_code 2
Config-register even parity on CR and DIVR → err_code 1, with reset-consistent parity shadows so no spurious fault fires before firmware’s first configuration write
Complementary-DMR bit-shift-counter lockstep catches a stuck or diverging shift-engine sequence → err_code 9, backed by an AP_CNT_LOCKSTEP_CLEAN SVA in simulation
DFT fault-injection ports (tx_ecc_inj / rx_ecc_inj) exercise SECDED correction and double-bit detection without a golden-vector testbench change
Catalog FMEDA (pre-sign-off engineering numbers): SPFM 95.10%, LFM 90.00%, PMHF 1.41×10⁻⁹/h — PASS against the ASIL-B target

Standards & Compliance

Winbond W25Q / Spansion S25FL / JEDEC SFDP NOR-flash command protocol; AMBA APB4; ISO 26262 ASIL-B SEooC (SPFM 95.10%, LFM 90.00%, PMHF 1.41×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 95.10% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
qspi #(
 .ADDR_W(6)
) u_qspi (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Quad-SPI Flash Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space