RV64 Dual-Core Lockstep CPU (DCLS, CVA6/CV64A6)

What it is

rv64_lockstep is a dual-core delay-compare lockstep (DCLS) wrapper around two vendored OpenHW CVA6 (CV64A6, RV64GC) safety cores: a CHECKER core replays the MAIN core’s input history LOCKSTEP_DELAY cycles behind it.

Key Features

• Dual OpenHW CVA6 (CV64A6, RV64GC) cores — each an rv64_safe instance — in delay-compare lockstep; parameterised LOCKSTEP_DELAY (default 2 cycles, minimum 1) sets the temporal-diversity window
• 475-bit compared bundle every cycle: the full noc_req_t AXI request (aw/w/ar channels + valids) plus each core’s own err_valid/err_code — any divergence raises err_code 9 + recover_req_o
• Comparator self-check: diverse dual compare (inequality + XOR-reduce, cross-checked, KEEP_ATTR) plus a periodic 16-cycle-interval walking-vector self-test across all 475 bits, closing the un-triplicated comparator (err_code 9)
• KEEP_ATTR-duplicated prime counter (DMR): a stuck-at on the bare prime FSM would otherwise silently blind the live compare forever; the duplicate’s divergence is itself a reported fault
• Own safety_monitor instance wires only lockstep_in — this wrapper’s err_code reports exclusively 9 (mismatch/comparator fault) or 0xF (monitor self-fault); the discrete AXI SLVERR/DECERR code is available separately from the underlying rv64_safe instance
• Unmodified vendored CVA6 RTL (Solderpad license) preserves OpenHW verification status; pin-compatible AXI “noc” port set with the catalog’s rv64_safe
• Measured FMEDA meets ASIL-D under the measured-DC overlay — SPFM 99.98%, LFM 100.00%, PMHF 6.73×10⁻⁹/h — comparator coverage substantiated by design-equivalence to the gate-level-FI-measured xs_lockstep comparator

Standards & Compliance

RV64GC (OpenHW CVA6/CV64A6 core, unmodified vendored Solderpad-licensed RTL), AXI4 “noc” bus protocol; ISO 26262 ASIL-D SEooC (measured-DC overlay: SPFM 99.98%, LFM 100.00%, PMHF 6.73×10⁻⁹/h), pairs with the rv64_safe ASIL-B substrate

Functional Safety

ASIL-D target (SEooC) · SPFM 99.98% · LFM 100.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
rv64_lockstep #(
 .ADDR_W(6)
) u_rv64_lockstep (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.