RV64 Register-File SECDED ECC

What it is

rv64_rf_ecc is a full-width 64-bit SECDED (Hamming + overall parity) shadow-ECC wrapper that non-invasively hardens the architectural integer register file of the vendored CVA6 (OpenHW CV64A6, RV64GC) core: single-bit upsets are corrected transparently on read, and uncorrectable double-bit upsets are flagged to the catalog safety_monitor as a register-file parity fault.

Key Features

• Full-width 64-bit SECDED code (ecc_pkg::ecc_enc64/ecc_dec64, 7 Hamming + 1 overall parity, 8 check bits/entry) — corrects any single bit in the 64-bit word, unlike a two-lane 32-bit split
• Drop-in, non-invasive wrapper: instantiates the real ariane_regfile unmodified, every port passed straight through — the Solderpad-licensed CVA6 core RTL is never edited
• Combinational per-port read-correct with zero added latency; write-side shadow mirrors the real regfile’s own commit-write decode (highest port wins on collision, x0 forced to the encode of 0)
• Double-bit upset → err_code 1 (register-file parity, the catalog’s highest-severity hardware code) via the shared safety_monitor; single-bit upset corrected + flagged (ecc_sbe_o) without raising a fault
• Read-side DFT fault injection (dft_inj_en/dft_inj_addr/dft_inj_xor) synthesizes SBE/DBE for diagnostic-coverage proof without corrupting the persistent shadow
• Both the real regfile and the shadow reset to a mutually consistent all-zero state — no SRAM-style uninitialized-array hazard to guard with a fill pass
• Measured/estimated FMEDA (informational): SPFM 92.10%, LFM 97.05%, PMHF 1.46×10⁻⁸/h — PASS ASIL-B; forms the rv64_safe substrate and is subsumed by rv64_lockstep’s DCLS for ASIL-D

Standards & Compliance

RV64GC (CVA6/OpenHW CV64A6 core, unmodified vendored RTL); ISO 26262 ASIL-B SEooC (informational, pre-sign-off) — SPFM 92.10%, LFM 97.05%, PMHF 1.46×10⁻⁸/h

Functional Safety

ASIL-B target (SEooC) · SPFM 92.10% · LFM 97.05% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
rv64_rf_ecc #(
 .ADDR_W(6)
) u_rv64_rf_ecc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.