Motor, Power & Sensor Control

SDFM — Sigma-Delta Filter Module

The digital decimation and fast-trip front end that turns an isolated ΔΣ current/voltage sensor’s 1-bit bitstream into a protected…

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ASIL-B

target

92.67%

SPFM

100.00%

LFM

PASS

FMEDA

24.0K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

SDFM — Sigma-Delta Filter Module routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

The digital decimation and fast-trip front end that turns an isolated ΔΣ current/voltage sensor’s 1-bit bitstream into a protected… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable digital decimation front-end for isolated sigma-delta (ΔΣ) modulators, delivered as synthesizable SystemVerilog soft-IP.

Key Features

Per-channel sinc³ (CIC) decimation of a 1-bit ΔΣ bitstream into a signed 32-bit reading; bit 1 → +1, bit 0 → −1 (bipolar), so a 50%-density stream reads ≈0 — natural for current sensing.
Up to NCH parallel channels (default 4) on one shared modulator clock sd_mclk, each consuming a single sd_d[ch] pin.
Runtime-programmable oversampling ratio (DOSR) per channel trades output bandwidth for noise floor; CIC DC gain ≈ DOSR³.
Per-channel signed HLT/LLT threshold compare drives a latched, structural sd_trip output wired directly to the PWM trip_n — independent of firmware, one-decimation-period latency.
Optional post-CIC 4-tap Hann FIR (FIR_EN) and PWM-edge sync reset (SYNC_EN) for coherent, smoothed sampling.
ASIL-B: sinc³ integrator complementary-shadow DMR (err_code 9) and config-register even parity (err_code 1) feed the shared safety_monitor; TRIPCLR rejects clearing while any channel remains over-range.
SPFM 92.67%, LFM 100.00%, PMHF 3.32×10⁻⁸/h — PASS ASIL-B (engineering FMEDA, 23,387-cell netlist).

Standards & Compliance

ISO 26262-5/-9 (ASIL-B SEooC); AMBA APB4

Functional Safety

ASIL-B (SEooC) · SPFM 92.67% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x04`	STATUS	RO [0]=TRIP, [NCH-1:0] in [8+:NCH] = per-ch over-range (live)
`0x08`	TRIPEN	[NCH-1:0] per-channel over-range -> TRIP enable
`0x0C`	TRIPCLR	W1: clear the latched TRIP (only once no channel is over-range)
`0x10`	IER	[0]=NEWDATA_IE [1]=TRIP_IE
`0x14`	ISR	RW1C [0]=NEWDATA(any ch) [1]=TRIP

…2 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
sdfm #(
 .ADDR_W(6)
) u_sdfm (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in motor drives, power conversion, and sensor front-ends in automotive and industrial systems.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SDFM — Sigma-Delta Filter Module?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space