Serial, Networking & Storage

SD / eMMC Host Controller (sdmmc)

APB4 SD/eMMC host controller for black-box logging and firmware storage — CRC-checked command and data transport, ASIL-B diagnosed, silicon-ready.

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ASIL-B

target

93.25%

SPFM

90.00%

LFM

PASS

FMEDA

5.1K

gates

10.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

SD / eMMC Host Controller (sdmmc) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

APB4 SD/eMMC host controller for black-box logging and firmware storage — CRC-checked command and data transport, ASIL-B diagnosed, silicon-ready. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable SD/eMMC host controller for non-volatile data logging and firmware/config storage in safety-relevant embedded systems, delivered as synthesizable SystemVerilog soft-IP.

Key Features

SD-mode CMD/RESP transceiver: 48-bit frame with CRC7, R1 (48-bit) and R2 (136-bit) response reception, CRC7-verified on R1
DAT-line block engine: 1-bit and 4-bit bus modes, per-lane CRC-16-CCITT, 32-byte SECDED-protected RX/TX FIFOs, configurable block length
Multi-block read/write (CMD18/CMD25) with automatic block re-arm and automatic CMD12 STOP_TRANSMISSION (AUTO_STOP_EN)
Card-detect and write-protect pad inputs with live STATUS bits, plus SDIO interrupt detection on DAT[1] while idle
ASIL-B: err_valid/err_code[3:0] — parity (1), FIFO SECDED DBE (2), CRC7/CRC16/status protocol (3), response timeout (4), CRC-flag DMR shadow (9)
Catalog FMEDA: SPFM 93.25%, LFM 90.00%, PMHF 6.46×10⁻⁹/h — PASS against ASIL-B, at 5,081 generic cells
Roadmap: 8-bit eMMC DAT bus, UHS-I DDR50 timing, eMMC boot mode

Standards & Compliance

SD Physical Layer Simplified Specification v6.0; JEDEC eMMC JESD84-B51 (eMMC v5.1); CRC7 / CRC-16-CCITT; ISO 26262 ASIL-B SEooC (SPFM 93.25%, LFM 90.00%, PMHF 6.46×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 93.25% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	W1: [0]=START [1]=RESP_LONG (R2, 136-bit) [2]=NO_RESP
`0x04`	STATUS	RO [0]=BUSY [1]=DONE [2]=CRC_ERR [3]=TIMEOUT [4]=CARD_PRESENT (= !cd_n_i) [5]=WRITE_PROTECT (= wp_i) (v9)
`0x08`	CLKDIV	sd_clk = clk / (2*(CLKDIV+1))
`0x0C`	CMD_IDX	[5:0] command index
`0x10`	CMD_ARG	32-bit argument

…4 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
sdmmc #(
 .ADDR_W(6)
) u_sdmmc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SD / eMMC Host Controller (sdmmc)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space