Cryptography & Data Integrity

SHA3-256 Hash Core

FIPS 202-verified SHA3-256/Keccak-f[1600] compute core with triple diverse-DMR self-checking…

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ASIL-B

target

99.97%

SPFM

100.00%

LFM

PASS

FMEDA

24.2K

gates

0.1.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

FIPS 202-verified SHA3-256/Keccak-f[1600] compute core with triple diverse-DMR self-checking… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A SHA3-256 (Keccak-f[1600]) hash core delivered as synthesizable SystemVerilog soft-IP, implementing FIPS 202 SHA3-256 (1088-bit rate, 512-bit capacity, 24-round Keccak-f[1600] permutation, one round per clock cycle).

Key Features

FIPS 202 SHA3-256: 1088-bit rate (17 × 64-bit lanes), 512-bit capacity, 256-bit digest
24-round Keccak-f[1600] permutation, one round/cycle → deterministic 24-cycle hash latency after start
Internal pad10*1 padding with SHA-3 domain byte 0x06; user supplies only the unpadded message (0–135 bytes) and length
Spatial DMR duplicates the entire 1600-bit permutation datapath (A vs A_shadow), compared every round — err_code 9
Independent-cone DMR on the round counter (round_cmpl) and the control FSM (state_cmpl) — err_code 9
ASIL B PASS: SPFM 99.97%, LFM 100.00%, PMHF 1.37×10⁻¹⁰ /h, proven by BMC (control graph) + simulated fault injection (datapath DMR)
Bare compute-core ports (no bus): drop-in behind a host FSM/DMA; optional periodic KAT closes the one shared-absorb-network residual

Standards & Compliance

FIPS 202 (SHA-3); ISO 26262 ASIL B (SEooC, PASS)

Functional Safety

ASIL-B (SEooC) · SPFM 99.97% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
sha3_256 #(
 .ADDR_W(6)
) u_sha3_256 (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SHA3-256 Hash Core?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space