Cryptography & Data Integrity

SHAKE-128/256 XOF

The FIPS 202 extendable-output function that drives every ML-KEM and ML-DSA hash/PRF step, with ASIL-B fault detection built in.

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ASIL-B

target

94.21%

SPFM

92.51%

LFM

Informational

FMEDA

11.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

The FIPS 202 extendable-output function that drives every ML-KEM and ML-DSA hash/PRF step, with ASIL-B fault detection built in. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

shake_xof is the extendable-output function (XOF) that post-quantum ML-KEM (Kyber, FIPS 203) and ML-DSA (Dilithium, FIPS 204) use for all of their hashing and pseudorandom generation.

Key Features

FIPS 202-exact SHAKE-128 (rate 168 B) and SHAKE-256 (rate 136 B) sponge, sharing the verified keccak_f1600 permutation with sha3_256
Single-block absorb (message ≤ rate−1 bytes) and multi-block squeeze up to 256 output bytes, matched byte-for-byte to Python hashlib
Direct byte-stream handshake (wr_en/wr_addr/wr_data in, rd_addr/rd_data out) built to feed mlkem_cbd (PRF noise) and sample_ntt (matrix XOF) with no bus fabric in between
Spatial DMR on the 1600-bit Keccak permutation — a shadow keccak_f1600 compared every cycle — → err_code 9
Duplicate-DMR control FSM (absorb/permute/squeeze sequencing) → err_code 9, plus a DFT-injectable parity path → err_code 1
ASIL-B SEooC FMEDA: SPFM 94.21%, LFM 92.51%, PMHF 1.98×10⁻⁸/h (informational Technology-Preview)
Bit-exact golden verification (tools/shake_xof_gold.py vs hashlib) across single/multi-block, short-output, empty-message, and fault-injection cases

Standards & Compliance

FIPS 202 (SHA-3/SHAKE); post-quantum PRF/XOF for NIST FIPS 203 ML-KEM and FIPS 204 ML-DSA; ISO 26262 ASIL-B (SEooC, informational Technology-Preview)

Functional Safety

ASIL-B target (SEooC) · SPFM 94.21% · LFM 92.51% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
shake_xof #(
 .ADDR_W(6)
) u_shake_xof (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SHAKE-128/256 XOF?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space