Avionics, Space & Mil-Std Networking

SpaceWire (ECSS-E-ST-50-12C) Link Controller

ECSS-E-ST-50-12C SpaceWire link controller — DS-encoded external link boundary, credit-flow-controlled, ASIL-B safety overlay.

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ASIL-B

target

97.77%

SPFM

99.00%

LFM

PASS

FMEDA

6.5K

gates

0.1.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

SpaceWire (ECSS-E-ST-50-12C) Link Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

ECSS-E-ST-50-12C SpaceWire link controller — DS-encoded external link boundary, credit-flow-controlled, ASIL-B safety overlay. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A configurable SpaceWire (ECSS-E-ST-50-12C) link controller delivered as synthesizable SystemVerilog soft-IP, implementing the Data-Strobe (DS) character/exchange-level protocol, credit-based flow control and the ECSS link-state machine on an APB4 register interface.

Key Features

DS (Data-Strobe) character/exchange-level protocol — NULL (ESC+FCT), FCT, Time-code (ESC+Data), N-Char, EOP/EEP, all with odd parity per char; spw_do/so and spw_di/si are LVDS-level signals for an external SpaceWire transceiver/connector — no on-chip analog PHY
Credit-based flow control: each received FCT grants 8 TX credits; this end issues an FCT only when its SECDED RX packet FIFO has real room for the 8 N-Chars it grants, so back-pressure is genuine FIFO occupancy, not a fixed window
Full ECSS-E-ST-50-12C link-state machine (ErrorReset→ErrorWait→Ready→Started→Connecting→Run) with autostart/link-start control; any protocol fault forces an automatic, firmware-free re-handshake
ECSS-exact §8.5.2.5 disconnect-detect: a formally verified 850 ns silence-window counter (DISCONNECT_CYC = round(850e-9 × f_clk)) declares the partner disconnected → err_code 3 + ErrorReset
SECDED-protected TX/RX packet FIFOs (fifo_ecc): single-bit upsets corrected transparently; an uncorrectable double-bit upset or pointer-DMR mismatch → err_code 2
Second clock domain on the recovered DS bit-clock (spw_rxclk = D xor S): the DS receive/decode runs there and crosses to the system clock through a shared gray-pointer async FIFO (cdc_fifo), no external synchronizer needed
ASIL-B safety overlay: config-register even parity (err_code 1), SECDED FIFOs (err_code 2), character-parity/ESC/credit/disconnect protocol checks (err_code 3), complementary-DMR link-FSM lockstep (err_code 9); companion spacewire_rmap adds end-to-end packet CRC

Standards & Compliance

ECSS-E-ST-50-12C SpaceWire; ISO 26262 ASIL-B SEooC

Functional Safety

ASIL-B (SEooC) · SPFM 97.77% · LFM 99.00% · PASS

ISO 26262-5 FMEDA method (transferable evidence for the ECSS-Q-ST-60 / radiation case) · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	0x04 STATUS 0x08 TXDIV 0x0C TXCHAR 0x10 RXCHAR
`0x14`	TIMECODE	0x18 IER 0x1C ISR(W1C) 0x20 ERR(W1C) [7]TX_FULL [6]RX_FULL [5]RX_DBE [4]RX_VALID [3]CREDIT_ERR [2]reserved [1]RUNNI…

Getting Started

// Minimal instantiation
spacewire #(
 .ADDR_W(6)
) u_spacewire (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in avionics, defense, and space systems built to the ARINC, MIL-STD, and CCSDS standards.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SpaceWire (ECSS-E-ST-50-12C) Link Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

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Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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