Serial, Networking & Storage

SPI Master Controller

A full-duplex SPI master controller delivered as synthesizable SystemVerilog soft-IP.

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ASIL-B

target

95.26%

SPFM

90.00%

LFM

PASS

FMEDA

2.0K

gates

1.5.0

version

The deliverable

What you’re licensing

A full-duplex SPI master controller delivered as synthesizable SystemVerilog soft-IP. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A full-duplex SPI master controller delivered as synthesizable SystemVerilog soft-IP.

Key Features

All four SPI modes (CPOL/CPHA 0-3), MSB- or LSB-first, selectable at runtime
Programmable SCK clock divider (16-bit DIVR half-period), shared bus-wide across every chip select
Up to 8 hardware one-hot chip selects (spi_cs_n) — no external CS decoder needed
Parameterized SECDED-protected TX/RX FIFOs (4-64 entries) with tx_dreq/rx_dreq DMA-request handshake
Back-to-back byte streaming: chip select stays asserted while the TX FIFO keeps draining
Config-register even parity (err_code 1) and FIFO SECDED double-bit detection (err_code 2)
Diverse-DMR complementary shadow on the transfer FSM and TX/RX shift registers (err_code 9); ASIL-B FMEDA: SPFM 95.26%, LFM 90.00%

Standards & Compliance

Motorola SPI / Freescale DSPI protocol (4-wire, modes 0-3); ISO 26262 ASIL-B SEooC (SPFM 95.26%, LFM 90.00%, PMHF 1.77×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 95.26% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CR:	[7]=EN [6]=CPHA [5]=CPOL [4]=MSBFIRST [1]=TXEIE [0]=RXNEIE
`0x04`	DIVR:	[15:0] SCK half-period in clk cycles (SCK period = 2×DIVR; 0=off)
`0x08`	CSR:	[0]=CS_EN (assert the selected chip select for the transfer) [3:1]=CS_SEL (0..NCS-1 — which of the up-to-8 chip selec…
`0x0C`	DR:	write=push TX FIFO; read=pop RX FIFO
`0x10`	SR:	[3]=BSY [2]=OVR [1]=RXNE [0]=TXE (read-only)

…1 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
spi_master #(
  .ADDR_W(6)
) u_spi_master (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SPI Master Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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