Serial, Networking & Storage

SPI Slave Controller

CPOL/CPHA SPI slave — 2-FF synchronized, CS-framed, ASIL-B lockstep.

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ASIL-B

target

98.99%

SPFM

100.00%

LFM

PASS

FMEDA

448

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

SPI Slave Controller routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

CPOL/CPHA SPI slave — 2-FF synchronized, CS-framed, ASIL-B lockstep. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

A synthesizable SPI slave (device) soft-IP — the counterpart to ip/spi_master. An external SPI master drives sclk/mosi/cs_n, asynchronous to the host clock; this IP synchronizes them, frames each transfer on chip-select, and shifts data in/out via APB4 TXDATA/RXDATA registers, supporting all four CPOL/CPHA modes.

Key Features

All 4 SPI modes (CPOL/CPHA), 8-bit MSB-first, parameterizable WORD_W
2-FF synchronizer on sclk/mosi/cs_n — the design’s only clock-domain crossing
CS-framed transfers: a synchronized cs_n assert resets the bit counter, RX shift register, and TX index every word
miso_en output-enable for tri-stating a shared/multi-drop MISO bus
APB4 TXDATA/RXDATA + RX_READY/OVERRUN status, maskable RX interrupt (spi_irq)
Config parity (err_code 1) + TX/RX data-register parity (err_code 2) via safety_monitor
Bit-counter / RX-shift complementary-DMR lockstep (err_code 9); ASIL-B FMEDA: SPFM 98.99%, LFM 100.00%

Standards & Compliance

Motorola/Freescale SPI protocol (4-wire, modes 0–3, CPOL/CPHA); ISO 26262 ASIL-B SEooC (SPFM 98.99%, LFM 100.00%, PMHF 8.55×10⁻¹¹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 98.99% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=CPOL [2]=CPHA
`0x04`	STATUS	[0]=RX_READY [1]=OVERRUN(W1C) [2]=CS_ACTIVE
`0x08`	TXDATA	0x0C RXDATA (read clears RX_READY) 0x10 IER [0]=RX_IE

Getting Started

// Minimal instantiation
spi_slave #(
 .ADDR_W(6)
) u_spi_slave (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in SPI Slave Controller?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space