Serial, Networking & Storage

10BASE-T1S PLCA Sublayer

IEEE 802.3cg Clause 148 multidrop transmit-opportunity arbiter.

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ASIL-B

target

91.15%

SPFM

90.00%

LFM

PASS

FMEDA

987

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

IEEE 802.3cg Clause 148 multidrop transmit-opportunity arbiter. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

t1s_plca is the PLCA (Physical Layer Collision Avoidance) reconciliation sublayer for 10BASE-T1S automotive single-pair Ethernet — the IEEE 802.3cg Clause 148 arbiter that makes the shared, half-duplex single pair collision-free.

Key Features

Full Cl.148 control state diagram — EARLY_RECEIVE / COMMIT / BURST / ABORT / RECOVER
Yield-on-idle: an unused slot costs ~2 cycles, so latency scales with OFFERED LOAD, not node count
EARLY_RECEIVE freezes the token for a frame longer than aTransmitOpportunityTimer — the segment cannot desync
BEACON/COMMIT as real xMII control symbols (TX_ER/RX_ER + codepoint), discrete beacon pin optional
Single-owner MAC→PHY gating — two nodes never drive the pair at once
Bursting: up to aMaxBurstCount frames inside one transmit opportunity
Per-node aLocalNodeID / aNodeCount / aTransmitOpportunityTimer / aMaxBurstCount (APB CSRs)
FSM + TO-token complementary DMR (err_code 9) — formally-proven single-owner grant (unbounded k-induction)
Collision / duplicate-node-ID protocol check (err_code 3), beacon-TO watchdog with RECOVER resync (err_code 4), config parity (err_code 1)
Verified on a 4-node mixing segment: 39/39 interop checks, never two drivers on the pair
xMII MAC-side ↔︎ PHY-side; grant drives eth_t1_mac’s plca_to_i, its plca_tx_req_o feeds packetPending

Standards & Compliance

IEEE 802.3cg Clause 148 (10BASE-T1S PLCA)

Functional Safety

ASIL-B (SEooC) · SPFM 91.15% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	PLCA_CTRL	[0]=PLCA_EN [1]=SW_RST(self-clear resync) [2]=BURST_EN [3]=XMII_BCN_EN RW
`0x04`	PLCA_STAT	RO [0]=SYNCED [1]=TO_ACTIVE [2]=TO_TMO(sticky) [3]=IS_COORD [4]=COLLIDED(sticky) [11:8]=state [19:16]=burst count
`0x08`	PLCA_ID	[7:0]=aLocalNodeID (0 = coordinator / beacon source) RW
`0x0C`	PLCA_NCNT	[7:0]=aNodeCount (number of nodes on the mixing segment) RW
`0x10`	PLCA_TOTMR	[7:0]=aTransmitOpportunityTimer (TO slot length, xMII cycles) RW

…4 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
t1s_plca #(
 .ADDR_W(6)
) u_t1s_plca (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in 10BASE-T1S PLCA Sublayer?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space