RISC-V Cores & SoC Platform

ECC Tightly-Coupled Memory (ITCM + DTCM)

The deterministic, single-cycle local memory for lockstep RISC-V safety cores — replaces the cache where timing analyzability and FMEDA closure…

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ASIL-B

target

93.86%

SPFM

100.00%

LFM

Informational

FMEDA

2.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

The deterministic, single-cycle local memory for lockstep RISC-V safety cores — replaces the cache where timing analyzability and FMEDA closure… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

tcm is a core-coupled ECC Tightly-Coupled Memory delivered as synthesizable SystemVerilog soft-IP.

Key Features

Two independent SECDED-protected banks — read-only ITCM (instruction) and read/write byte-enabled DTCM (data), each DEPTH-deep × 32-bit, single-cycle, always-grant, fully deterministic OBI-lite ports
On-the-fly SECDED correct/detect per word (ecc_pkg, 7 check bits): single-bit upsets corrected and counted (ISEC/DSEC); a double-bit error raises err_code 2 with bank + address captured in ERRINFO/ERRADDR
Background scrubber walks idle host-port cycles, healing a latent single-bit error before a second upset can pair it into an uncorrectable double — the FMEDA’s dominant latent-fault reducer
Byte-enabled DTCM writes are read-modify-write, so a sub-word store still re-encodes a full-word SECDED codeword
Config-register even-parity on scrub-enable (err_code 1) and an address out-of-range plausibility check against the populated bank window (err_code 3)
KEEP_ATTR complementary-DMR shadow on the scrub/access-control FSM catches a control-logic fault the SECDED datapath alone cannot see (err_code 9)
fi_i_req/fi_d_req DFT fault-injection ports XOR a mask into a stored ITCM or DTCM codeword to prove SBE correction and DBE detection in a diagnostic-coverage campaign; tie 0 in mission mode

Standards & Compliance

OBI-lite core ports, APB4-lite config/status; ISO 26262 ASIL-B SEooC (SPFM 93.86%, LFM 100.00%, PMHF 8.86×10⁻⁹/h)

Functional Safety

ASIL-B target (SEooC) · SPFM 93.86% · LFM 100.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=SCRUB_EN (background scrubber enable)
`0x04`	STATUS	[1]=SCRUB_BUSY (RO) [0]=ERR (RO, monitor err_valid)
`0x08`	ISEC	ITCM corrected single-bit-error count (RO)
`0x0C`	IDED	ITCM detected double-bit-error count (RO)
`0x10`	DSEC	DTCM corrected single-bit-error count (RO)

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
tcm #(
 .ADDR_W(6)
) u_tcm (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in ECC Tightly-Coupled Memory (ITCM + DTCM)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space