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Teleop Link Guard — Command-Link Freshness Watchdog

The operator-side freshness watchdog for a teleoperated command/video link — catches the stale, frozen, dropped…

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ASIL-B
target
99.65%
SPFM
91.31%
LFM
Informational
FMEDA
1.8K
gates
1.0.0
version
Interfaces at a glance

Block diagram

teleop_link_guard19 portsapb_slave8 signalsframe_*4 signalslocal_timesafe_state_oclkrst_nsafety / statuserr_clear · err_valid · err_code
Place-and-route snapshot

Physical implementation

Teleop Link Guard — Command-Link Freshness Watchdog routed place-and-route layout on the Nangate45 PDK
A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.
The deliverable

What you’re licensing

The operator-side freshness watchdog for a teleoperated command/video link — catches the stale, frozen, dropped… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

teleop_link_guard is the operator/decoder-side freshness watchdog for a teleoperated video link, delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-B) safety instrumentation.

Key Features

Standards & Compliance

ISO 26262 ASIL-B SEooC (pre-sign-off, D4 gate-level measured: SPFM 99.65%, LFM 91.31%, PMHF 0/h); AMBA APB4-lite control/status; IEEE 802.1AS time-sync (AoU for the latency check); Technology Preview — digital-only, silicon validation pending, FMEDA informational

Functional Safety

ASIL-B target (SEooC) · SPFM 99.65% · LFM 91.31% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

OffsetRegisterDescription
0x00CTRLRW [0]=EN, [1]=SEQ_CHK, [2]=FRZ_CHK, [3]=LAT_CHK
0x04LAT_BUDGETRW [31:0] max glass-to-glass latency / staleness age (time-base units; 0=off)
0x08FRAME_TORW [31:0] max cycles between decoded frames (no-frame watchdog; 0=off)
0x0CFRZ_NRW [7:0] freeze threshold (consecutive identical frame hashes)
0x10STATUSRO [0]=STALE, [1]=NOFRAME, [2]=SEQGAP, [3]=FREEZE, [4]=SAFE_STATE, [5]=ERR_VALID, [9:6]=ERR_CODE

…3 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
teleop_link_guard #(
 .ADDR_W(6)
) u_teleop_link_guard (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in UAV flight controllers and robotics platforms operating under a functional-safety mandate.

The case

Why license it, not build it

Skip 12–18 months
The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.
One vendor, one safety story
Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.
Verified, not vapor
The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Teleop Link Guard — Command-Link Freshness Watchdog?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space