AI Inference & Acceleration

Tile Compute — Tileable RISC-V + MAC Compute-Tile Engine

A programmable, ASIL-B safety-rated compute tile — N DCLS RISC-V + ai_mac lanes sharing an ECC L2 — the control-plus-compute member of a tiled-GEMM /…

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ASIL-B

target

94.69%

SPFM

90.00%

LFM

Informational

FMEDA

295K

gates

1.0.0

version

Interfaces at a glance

Block diagram

The deliverable

What you’re licensing

A programmable, ASIL-B safety-rated compute tile — N DCLS RISC-V + ai_mac lanes sharing an ECC L2 — the control-plus-compute member of a tiled-GEMM /… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

tile_compute is a tileable, safety-rated compute-tile engine for an AI-accelerator subsystem: N lanes, each a dual-core-lockstep (DCLS) RISC-V32 core plus an ABFT ai_mac, share one ECC-protected L2 scratchpad.

Key Features

N tileable compute lanes (default 3), each a DCLS RISC-V32 core (rv32_lockstep, 2× CV32E40S) plus an ABFT ai_mac, sharing one ECC-protected L2 via a round-robin TL-UL fabric.
Host/DMA-fed scratchpad model: dedicated l2_we/l2_waddr/l2_wdata preload port and a broadcast lane_start/base_addr — no operand data ever crosses the APB4 config plane.
Each lane MAC-accumulates a K-word contraction slice per pass — the partial-sum primitive of a blocked/tiled GEMM — with N lanes in parallel realizing M-way output tiling.
Config/address parity check per lane → err_code 1; independent duplicate-sum ABFT on the MAC accumulator → err_code 2; duplicate-DMR shadow of the compute FSM (DCLS core-compare stand-in) → err_code 9.
Per-tile safety island: safety_monitor first-event latch aggregates every lane’s fault into one tile err_code; fccu adds a TMR-voted sticky aggregate with graded Low/High/Critical fault_out_o reaction.
Deterministic, bit-exact round-robin arbitration to the shared ecc_sram L2 (SECDED + background scrub) — no non-determinism in lane-to-L2 routing.
ASIL-B SEooC (SPFM 94.69%, LFM 90.00%, informational Technology-Preview) built almost entirely from catalog reuse (rv32_lockstep, ai_mac, ecc_sram, fccu, safety_monitor).

Standards & Compliance

ISO 26262 ASIL-B SEooC (informational Technology-Preview); AMBA APB4 (config plane); tileable RISC-V32 (CV32E40S DCLS) + INT8/INT32 MAC compute fabric

Functional Safety

ASIL-B target (SEooC) · SPFM 94.69% · LFM 90.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
tile_compute #(
 .ADDR_W(6)
) u_tile_compute (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in safety-critical edge inference — ADAS, autonomous robotics, and machine vision.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Tile Compute — Tileable RISC-V + MAC Compute-Tile Engine?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space