The deliverable
What you’re licensing
tlsafety is a composable end-to-end data-integrity codec for a TileLink link: it adds single-bit parity (ASIL-B) or SECDED ECC (ASIL-D-leaning)… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:
Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.
What it is
tl_safety is a composable end-to-end data-integrity codec for a TileLink link: it adds single-bit parity (ASIL-B) or SECDED ECC (ASIL-D-leaning) protection to the 32-bit TL data payload — protection TileLink itself does not provide, so a bit-flip on a TL data beat would otherwise be silent.
Key Features
- Single MODE_ECC parameter switches the whole codec: even parity (1 check bit, detect-only, ASIL-B) or 7-bit SECDED Hamming (single-bit correct / double-bit detect, ASIL-D-leaning) over the 32-bit gen_data/chk_data payload
- Generator (gen_data → gen_check[6:0]) and checker (chk_valid/chk_data/chk_check → chk_data_out/chk_err/chk_corrected) datapath in one module — instantiate one at each end of a TileLink hop and compose in front of any bridge without forking its RTL
- Check word rides as sideband alongside the TL channel (TL-UL/UH has no spare field for it); route chk_err into the bridge’s TileLink-D d_corrupt/d_denied and consume the corrected chk_data_out downstream
- Uncorrectable payload corruption → safety_monitor datapath fault (err_code=2); the monitor is itself dual-rail self-checking (reports 0xF on an internal fault)
- APB4 sidecar register file (CTRL/SR/ECNT, 4-byte stride): CTRL.EN gates fault logging, SR carries sticky UNCORR/CORR (W1C) plus read-only MODE_ECC, ECNT counts corrected single-bit events — the codec’s detect/correct path itself runs regardless of CTRL.EN
- Formally verified (SymbiYosys BMC): err_valid stays 0 on any round-trip-consistent beat, and err_valid=1 implies err_code is 2 or 0xF; mode-aware bit-exact TB (tb_tl_safety.cpp, make tlsafety) covers clean/single-bit/double-bit/check-bit-flip cases in both modes
- Catalog FMEDA (doc/fmeda/tl_safety_fmeda_report.md): ASIL-B SEooC, SPFM 98.10%, LFM 90.00%, PMHF 2.16×10⁻¹⁰/h — PASS with margin on every metric; honestly scoped v0.1: no protocol/timeout/opcode checking (safety_monitor’s protocol/timeout/corrupt/denied inputs tied to 0)
Standards & Compliance
TileLink UL/UH (payload sideband integrity codec, composable with any TL bridge); ISO 26262 ASIL-B SEooC (SPFM 98.10%, LFM 90.00%, PMHF 2.16×10⁻¹⁰/h)
Functional Safety
ASIL-B (SEooC) · SPFM 98.10% · LFM 90.00% · PASS
ISO 26262:2018 · FMEDA available · Safety Manual included
Register Map
| Offset | Register | Description |
|---|
0x00 | CTRL | [0]=EN |
0x04 | SR | [0]=UNCORR (W1C) [1]=CORR (W1C) [2]=MODE_ECC (RO) |
0x08 | ECNT | corrected-error count (RO, ECC mode) |
Getting Started
// Minimal instantiation
tl_safety #(
.ADDR_W(6)
) u_tl_safety (
.clk (clk),
.rst_n (rst_n),
// APB4
.p_paddr (paddr),
.p_psel (psel),
.p_penable (penable),
.p_pwrite (pwrite),
.p_pwdata (pwdata),
.p_prdata (prdata),
.p_pready (pready),
// Safety
.err_clear (1'b0),
.err_valid (err_valid),
.err_code (err_code)
);
Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.
Applications
Where it fits
Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.