System, Safety & Compute

TileLink Trace Port Monitor

tltpm (TileLink Trace Port Monitor) is a non-intrusive, read-only tap on a TileLink-UL (TL-UL) bus: it observes the A (request) and D (response)…

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ASIL-B

target

92.28%

SPFM

90.63%

LFM

PASS

FMEDA

5.2K

gates

0.4.0

version

The deliverable

What you’re licensing

tltpm (TileLink Trace Port Monitor) is a non-intrusive, read-only tap on a TileLink-UL (TL-UL) bus: it observes the A (request) and D (response)… It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

tl_tpm (TileLink Trace Port Monitor) is a non-intrusive, read-only tap on a TileLink-UL (TL-UL) bus: it observes the A (request) and D (response) channels only and never drives them, so inserting it cannot perturb the traffic it watches.

Key Features

Fully non-intrusive A/D-channel tap: every tl_a_/tl_d_ port including both *_ready handshakes is an input, so the monitor cannot alter or stall the bus it observes
Per-transaction trace record (timestamp, A-opcode, D-opcode, denied flag, source, address) assembled from a pending FIFO on the A-beat, completed by the matching in-order D-beat
Header/metadata tracer, not a data logger — no tl_a_data/tl_d_data port, so payload contents are never captured, keeping the trace path small and non-sensitive
8-bit inline SECDED (ecc_pkg) on every stored trace record: single-bit upsets corrected transparently on read-out, double-bit errors flagged err_code 2
Trace-FIFO write-pointer complementary diverse-DMR shadow catches a permanent or transient fault in the pointer logic itself — err_code 9
Bus-hang watchdog: a shared timeout_monitor raises err_code 4 if the pending FIFO stays non-empty (a captured request whose response never returns) past a configurable cycle count
Compact APB4 CSR block — CTRL 0x00 (EN/CLR), STATUS 0x0C, TRACE_LO 0x10, TRACE_HI 0x14 (reading TRACE_HI pops the head record) — plus config-register even parity, err_code 1

Standards & Compliance

SiFive TileLink Uncached-Lightweight (TL-UL); AMBA APB4 (read-out/config); ISO 26262 ASIL-B SEooC (SPFM 92.28%, LFM 90.63%, PMHF 8.40×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 92.28% · LFM 90.63% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	RW [0]=EN (capture) [1]=CLR (pulse: flush the trace + pending FIFOs)
`0x0C`	STATUS	RO [3:0]=trace count [4]=overflow [5]=pending!=0 [10:8]=err_code [11]=err_valid
`0x10`	TRACE_LO	RO head record: [15:0]=timestamp [18:16]=a_opcode [21:19]=d_opcode [22]=denied [26:23]=source
`0x14`	TRACE_HI	RO head record: [ADDR_W-1:0]=address; READING THIS POPS the head entry

Getting Started

// Minimal instantiation
tl_tpm #(
  .ADDR_W(6)
) u_tl_tpm (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in TileLink Trace Port Monitor?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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