TL-UL to AXI4-Lite Bridge

What it is

A single-outstanding protocol bridge that translates TileLink Uncached Lightweight (TL-UL) GET/PUT_FULL/PUT_PARTIAL transactions into AMBA AXI4-Lite AR/R and AW+W/B transfers, delivered as synthesizable SystemVerilog soft-IP.

Key Features

• TL-UL GET (opcode 4) / PUT_FULL (0) / PUT_PARTIAL (1), single-beat, single-outstanding
• Full AXI4-Lite 5-channel handshake: AR/R reads, simultaneous AW+W/B writes with independent aw_done/w_done completion tracking
• Single clock domain, no internal CDC — verified from the RTL (one clk/rst_n pair); external CDC required for a cross-clock AXI subordinate
• Configurable TIMEOUT_CYCLES watchdog: stalled AXI subordinate synthesizes a TL-D denied response (err_code 4)
• SECDED (39,32) G-9 on write-data and read-data lanes (err_code 2) + address/source config parity (err_code 1)
• Diverse-DMR complementary-redundant FSM lockstep on the 6-state protocol FSM (err_code 9)
• ASIL-B FMEDA: SPFM 91.80%, LFM 89.35%, PMHF 2.08×10⁻⁹/h; 100% formal mutation-kill rate

Standards & Compliance

TileLink Uncached Lightweight (TL-UL); AMBA AXI4-Lite; ISO 26262 ASIL-B SEooC (SPFM 91.80%, LFM 89.35%, PMHF 2.08×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.80% · LFM 89.35% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
tl_ul_to_axi4lite #(
  .ADDR_W(6)
) u_tl_ul_to_axi4lite (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.