Bus Bridges & Interconnect

TL-UL to Wishbone B4 Bridge

TileLink-UL subordinate to Wishbone B4 manager protocol bridge — single-clock, single-outstanding, ASIL-B safety layer.

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ASIL-B

target

91.80%

SPFM

89.35%

LFM

PASS

FMEDA

1.2K

gates

1.3.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

TL-UL to Wishbone B4 Bridge routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

TileLink-UL subordinate to Wishbone B4 manager protocol bridge — single-clock, single-outstanding, ASIL-B safety layer. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A one-way protocol bridge that converts TileLink-UL single-beat requests into Wishbone B4 classic single-beat bus cycles, delivered as synthesizable SystemVerilog soft-IP.

Key Features

Single-outstanding TL-UL GET/PUT_FULL/PUT_PARTIAL → Wishbone B4 classic single-beat translation via a three-state FSM (IDLE→ACTIVE→RESPOND); CYC and STB asserted and de-asserted together, never split into a pipelined burst
Single clock domain, no CDC: the saved-request registers, FSM, and safety monitor all run off one clk/rst_n pair — verified directly against the RTL port list and the absence of a tl_ul_to_wb entry in the CDC catalog
Configurable TIMEOUT_CYCLES watchdog (default 256) catches a non-responding Wishbone slave and forces tl_d_denied (+tl_d_corrupt on a GET) plus err_code 4, instead of hanging the fabric indefinitely
SECDED ECC (Hsiao code, ecc_pkg) on both the write-data and read-data pipeline registers — single-bit errors corrected transparently, double-bit errors flagged err_code 2
Even parity on the latched address/source (saved_addr_q/saved_source_q), checked outside IDLE — err_code 1 on a config-register upset
Complementary-redundant diverse-DMR FSM lockstep: an independent next-state cone recomputes the state from ~state_cmpl_q and flags any divergence from the live FSM — err_code 9
Catalog FMEDA (pre-sign-off engineering numbers): SPFM 91.80%, LFM 89.35%, PMHF 1.92×10⁻⁹/h — PASS against the ASIL-B target with margin on every metric

Standards & Compliance

TileLink Uncached-Lightweight (TL-UL); Wishbone B4 (OpenCores); ISO 26262 ASIL-B SEooC (SPFM 91.80%, LFM 89.35%, PMHF 1.92×10⁻⁹/h)

Functional Safety

ASIL-B (SEooC) · SPFM 91.80% · LFM 89.35% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
tl_ul_to_wb #(
 .ADDR_W(6)
) u_tl_ul_to_wb (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in heterogeneous SoCs that mix AMBA and TileLink IP and need clean, verified protocol and clock-domain crossings.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in TL-UL to Wishbone B4 Bridge?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space