System, Safety & Compute

Trace Encoder (trace_enc)

APB4 RISC-V branch-trace encoder that turns retired-instruction flow into compressed, loss-detected debug evidence with ASIL-B diagnostics.

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ASIL-B

target

100.00%

SPFM

90.00%

LFM

PASS

FMEDA

2.4K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

Trace Encoder (trace_enc) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

APB4 RISC-V branch-trace encoder that turns retired-instruction flow into compressed, loss-detected debug evidence with ASIL-B diagnostics. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

Trace Enc — Introduction

What it is

RISC-V branch-trace encoder (N-Trace/Nexus-style) with an APB4 slave interface and ASIL-B safety monitor.

Key Features

Discontinuity-only packet compression — SYNC/BRANCH/INDIRECT/TRAP packets, with straight-line execution folded into a per-packet icnt run length for high compression on typical code
Dedicated, same-clock trace-input tap (iretire/itype/iaddr) off the CPU retirement stage, decoupled from the APB4 config/read-out plane so debug traffic never contends with the bus
Sticky overflow / dropped-packet detection (STATUS.OVERFLOW, ISR.OVF, err_code 3) when a new discontinuity arrives while the 2-word emit buffer is still draining — loss is reported, never silent
APB4 slave register map — CTRL/STATUS/PACKET/COUNT/IER/ISR — plus a combined trace_irq (NOTEMPTY/OVF) for interrupt-driven drain
ASIL-B diagnostics: even-parity shadow on CTRL/IER (err_code 1) and an independent-DMR shadow of the icnt accumulator (err_code 9), both fed through the shared safety_monitor
err_clear/err_valid/err_code[3:0] safety ports for SoC fault-aggregator integration, active whenever CTRL.EN regardless of trace read-out activity
FMEDA-verified: SPFM 100%, LFM 90% — ASIL-B PASS; 25/25 Verilator smoke tests covering packet generation, icnt compression, forced resync, overflow, and the safety err_valid/err_clear path

Standards & Compliance

AMBA APB4 (ARM IHI 0024); RISC-V N-Trace / Nexus-style compressed branch trace; ISO 26262 ASIL-B SEooC (SPFM 100%, LFM 90%)

Functional Safety

ASIL-B (SEooC) · SPFM 100.00% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=EN [1]=SYNC_REQ (self-clearing) [2]=FIFO_RST (self-clearing)
`0x04`	STATUS	[0]=FIFO_EMPTY [1]=FIFO_FULL [2]=OVERFLOW (sticky, W1C via ISR)
`0x08`	PACKET	(RO) pop one 32-bit packet word (0 when empty)
`0x0C`	COUNT	(RO) number of words currently in the FIFO
`0x10`	IER	[0]=NOTEMPTY_IE [1]=OVF_IE

…1 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
trace_enc #(
 .ADDR_W(6)
) u_trace_enc (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in the safety backbone of an ASIL SoC — error detection, redundancy, and the fault-reaction path that takes the system to a safe state.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in Trace Encoder (trace_enc)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space