Cryptography & Data Integrity

TRNG

A digital conditioning and health-test front-end for a physical entropy source, delivered as synthesizable SystemVerilog.

Request this IP →Browse the catalog

ASIL-B

target

93.00%

SPFM

90.00%

LFM

PASS

FMEDA

1.8K

gates

0.1.0

version

The deliverable

What you’re licensing

A digital conditioning and health-test front-end for a physical entropy source, delivered as synthesizable SystemVerilog. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.

What it is

A digital conditioning and health-test front-end for a physical entropy source, delivered as synthesizable SystemVerilog.

Key Features

128-bit LFSR conditioning pool (x^128+x^29+x^27+x^2+1) folds each valid noise sample, with even-parity tracking (pool_par)
NIST SP 800-90B Repetition Count Test — stuck/dead source detection, parameterizable RCT_CUTOFF (default 32)
NIST SP 800-90B Adaptive Proportion Test — biased source detection, parameterizable APT_WINDOW/APT_CUTOFF (default 512/410)
ready_o hardware gate: RAND returns 0x0 unless the pool is seeded (SEED_BITS) and both health tests pass
APB4 slave: CTRL (0x00 enable), STATUS (0x04 ready/rct_fail/apt_fail/seeded), RAND (0x08, 32 conditioned bits, pool-stirring read)
ASIL-B: health-test trip is the dangerous-detected event → err_code 1; RCT/APT counters carry complementary DMR shadows → err_code 9 on divergence
Engineering FMEDA: SPFM 93.00%, LFM 90.00%, PMHF 2.21×10⁻⁹/h — PASS ASIL-B; 1015 LUTs on xcu200 (Vivado 2022.1)

Standards & Compliance

NIST SP 800-90B (continuous health tests: RCT, APT); ISO 26262 ASIL-B (SEooC, engineering FMEDA)

Functional Safety

ASIL-B (SEooC) · SPFM 93.00% · LFM 90.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=enable
`0x04`	STATUS	[0]=ready [1]=rct_fail [2]=apt_fail [3]=seeded
`0x08`	RAND	read = 32 conditioned bits (advances the pool when ready)

Getting Started

// Minimal instantiation
trng #(
  .ADDR_W(6)
) u_trng (
  .clk       (clk),
  .rst_n     (rst_n),
  // APB4
  .p_paddr   (paddr),
  .p_psel    (psel),
  .p_penable (penable),
  .p_pwrite  (pwrite),
  .p_pwdata  (pwdata),
  .p_prdata  (prdata),
  .p_pready  (pready),
  // Safety
  .err_clear (1'b0),
  .err_valid (err_valid),
  .err_code  (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in secure boot, firmware authentication, key storage, and confidential on-board communication.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in TRNG?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space