Serial, Networking & Storage

TSN 802.1Qbv Time-Aware Switch

3-port TSN L2 store-and-forward switch core with an IEEE 802.1Qbv Time-Aware Shaper for deterministic zonal Ethernet backbones; ISO 26262 ASIL-B SEooC.

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ASIL-B

target

91.00%

SPFM

90.00%

LFM

Informational

FMEDA

3.6K

gates

1.0.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

TSN 802.1Qbv Time-Aware Switch routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

3-port TSN L2 store-and-forward switch core with an IEEE 802.1Qbv Time-Aware Shaper for deterministic zonal Ethernet backbones; ISO 26262 ASIL-B SEooC. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

tsn_switch is a 3-port Time-Sensitive-Networking (TSN) L2 store-and-forward Ethernet switch with an IEEE 802.1Qbv Time-Aware Shaper (TAS), delivered as synthesizable SystemVerilog soft-IP with an APB4-lite control interface and built-in ISO 26262 (ASIL-B) safety instrumentation.

Key Features

3-port (parametric NUM_PORTS) L2 store-and-forward core at the frame-descriptor layer {da,sa,vlan,prio,len} — pairs with gmac for the payload datapath
MAC-address learning in an 8-entry CAM (MAC_ENTRIES): source learning on ingress, destination lookup for forwarding, round-robin victim eviction on a full table
Split-horizon unicast forwarding to the learned egress port; automatic flood to all other ports on an unknown DA or an all-ones broadcast DA
IEEE 802.1Qbv Time-Aware Shaper: free-running gate-cycle counter, a 4-entry Gate-Control-List ({interval,gate_states} per entry), gPTP-synced tick_i time reference
Fail-safe time-sync watchdog: no tick_i within SYNC_TMO forces every gate closed and freezes the gate counter rather than forwarding on stale schedule state
Six safety mechanisms feeding the shared safety_monitor: config/MAC-table parity (err_code 1), forwarding/queue plausibility + gate-schedule-integrity (err_code 3), time-sync timeout (err_code 4), forwarding-FSM/gate-counter DMR (err_code 9), plus fi_* DFT fault injection per mechanism
Measured FMEDA (pre-sign-off, informational): SPFM 91.00%, LFM 90.00%, PMHF 6.10×10⁻⁹/h — PASS ASIL-B

Standards & Compliance

IEEE 802.1Qbv Time-Aware Shaper; IEEE 802.1Q VLAN/priority; AMBA APB4-lite; ISO 26262 ASIL-B SEooC (SPFM 91.00%, LFM 90.00%, PMHF 6.10×10⁻⁹/h)

Functional Safety

ASIL-B target (SEooC) · SPFM 91.00% · LFM 90.00% · Informational — not gated

Informational FMEDA — this IP is reported but NOT gated. The SPFM/LFM figures above are engineering estimates from a model that is not held to the ASIL metric gates (QM, safety-by-composition, a vendor-core overlay, or a pre-sign-off Technology Preview, depending on the IP). They are not a certification claim and must not be relied on as one. See the safety manual for this IP’s exact status, assumptions of use, and any open items.

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

Offset	Register	Description
`0x00`	CTRL	[0]=SWITCH_EN [1]=TAS_EN (TAS_EN gates the 802.1Qbv shaper)
`0x04`	STATUS	RO [0]=SWITCH_EN [1]=TAS_EN [2]=SYNC_TIMEOUT [3]=Q_OVF [4]=FLOOD_LAST [7:5]=ACTIVE_GCL_IDX [10:8]=GATE_STATES
`0x08`	GATE_CYCLE	RW: gate-cycle period in clocks (the 802.1Qbv hyperperiod)
`0x0C`	SYNC_TMO	RW: max clocks between tick_i strobes (time-sync watchdog)
`0x10`	MACCFG	RW: [7:0]=our switch MAC low byte (modelled VLAN/admin)

…9 more registers — see datasheet for the full table.

Getting Started

// Minimal instantiation
tsn_switch #(
 .ADDR_W(6)
) u_tsn_switch (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in in-vehicle networks, industrial gateways, and sensor/actuator links where a bus controller has to carry its own safety argument.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in TSN 802.1Qbv Time-Aware Switch?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

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