RISC-V Cores & SoC Platform

XiangShan DCLS Lockstep Comparator (Core-Agnostic Overlay)

Core-agnostic dual-core delay-compare lockstep (DCLS) comparator that lifts a real XiangShan out-of-order RISC-V core pair to ISO 26262 ASIL-D…

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ASIL-D

target

99.96%

SPFM

100.00%

LFM

PASS

FMEDA

1600K

gates

0.1.0

version

Interfaces at a glance

Block diagram

Place-and-route snapshot

Physical implementation

XiangShan DCLS Lockstep Comparator (Core-Agnostic Overlay) routed place-and-route layout on the Nangate45 PDK — A real synthesis and place-and-route pass on this RTL, routed on the open Nangate45 / FreePDK45 PDK — evidence the block closes physically, not just in simulation. Target-PDK timing, area, and power sign-off figures are shared under NDA.

The deliverable

What you’re licensing

Core-agnostic dual-core delay-compare lockstep (DCLS) comparator that lifts a real XiangShan out-of-order RISC-V core pair to ISO 26262 ASIL-D… It is delivered as a licensable soft-IP block engineered as an ASIL-D Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:

Synthesizable RTL

Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.

Per-IP FMEDA report

SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.

Safety manual

Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.

IP-XACT + integration docs

A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.

Self-checking testbench

A self-checking testbench and a one-command build, so you can reproduce every claim on day one.

What it is

xs_lockstep is a core-agnostic dual-core delay-compare lockstep (DCLS) comparator that adds ASIL-D-class fault detection to a redundant pair of out-of-order RISC-V cores — including a real XiangShan (Nanhu/Kunminghu) generation — without vendoring or modifying a single line of the core’s RTL.

Key Features

Pure comparator overlay — no core instances, no vendored RTL; parametrized IN_W (checker-input width) / OUT_W (architectural compare width) / DELAY (checker lag, ≥ 1 cycle)
Binds to any XiangShan generation (or other OOO core pair) via the integrator’s own checkout — XS_RTL=<your>/XiangShan/build/rtl — with zero third-party redistribution to license
Diverse dual-path comparator (arithmetic inequality + XOR-reduce, cross-checked, KEEP_ATTR) plus a periodic walking-vector self-test sweeping every compared bit — closes the who-checks-the-checker single point (err_code 9)
KEEP_ATTR-duplicated prime counter (DMR): a stuck-at on the bare prime FSM would otherwise silently blind the live compare; the duplicate divergence is itself a reported fault
Gate-level fault-injection campaign measures the comparator + prime-FSM region at 100% detected / 0 dangerous — the single biggest lever behind the ASIL-D closure
lockstep_err (combinational) + recover_req (pulse) on divergence once primed (DELAY+1 cycles from reset); embedded SymbiYosys formal set confirmed vacuity-clean (err_valid/err_code both non-vacuously exercised)
Composes into xs_safety_island alongside xs_prf_ecc/xs_rob_parity/xs_iq_parity/xs_stq_parity for the full error taxonomy, with an explicit subsumption rule so per-structure single-point DC is never double-counted against the whole-pair DCLS DC

Standards & Compliance

RISC-V (core-agnostic OOO comparator; proven against a real XiangShan Nanhu/Kunminghu binding); ISO 26262 ASIL-D SEooC (gated, pre-silicon) — standalone SPFM 99.96% / LFM 100.00% / PMHF 8.97×10⁻⁹/h; composed xiangshan_lockstep SKU SPFM 99.96% / LFM 100.00% / PMHF 8.97×10⁻⁹/h

Functional Safety

ASIL-D (SEooC) · SPFM 99.96% · LFM 100.00% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
xs_lockstep #(
 .ADDR_W(6)
) u_xs_lockstep (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.

Applications

Where it fits

Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.

The case

Why license it, not build it

Skip 12–18 months

The FMEDA and the safety case are already generated. You integrate a finished safety element — you don’t stand up a safety-IP program to originate one.

One vendor, one safety story

Every block in the catalog shares the same safety architecture, fault-reaction model, and FMEDA methodology — so subsystems roll up cleanly.

Verified, not vapor

The RTL builds and passes today; the safety metrics come from analysis and fault injection against real RTL, not a datasheet promise.

Interested in XiangShan DCLS Lockstep Comparator (Core-Agnostic Overlay)?

Pricing, the per-IP FMEDA, safety manual, and RTL data room are shared under a mutual NDA.

Talk to us →See related IP

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space