The deliverable
What you’re licensing
SECDED-protected physical register file for an out-of-order RISC-V core. It is delivered as a licensable soft-IP block engineered as an ASIL-B Safety Element out of Context — not just RTL, but the complete functional-safety work package needed to carry it into an ISO 26262 program:
Synthesizable RTL
Portable, vendor-neutral SystemVerilog that drops onto your existing SoC fabric — no foundry or EDA-tool lock-in.
Per-IP FMEDA report
SPFM / LFM / PMHF computed against the ASIL target per ISO 26262-5 — the quantitative analysis your assessor asks for.
Safety manual
Assumptions of use, the safety mechanisms and their diagnostic coverage — written to drop straight into your safety case.
IP-XACT + integration docs
A machine-readable descriptor plus register and integration documentation for fast, low-risk bring-up.
Self-checking testbench
A self-checking (crypto: bit-exact) testbench and a one-command build, so you can reproduce every claim on day one.
SECDED-protected physical register file for an out-of-order RISC-V core.
Key Features
- Per-lane SECDED via the shared ecc_pkg codec (6 Hamming + 1 overall-parity check bit per 32-bit lane) — a single-bit upset in either lane of a register is corrected independently
- Combinational read-correct on all RD_PORTS (default 2) ports — decoded/corrected data is available the same cycle as the read address, no added latency
- Single encode-on-write port (we/waddr/wdata) — every store re-encodes both lanes, so the array is never left with an unprotected entry
- Background scrub pointer sweeps all NREGS entries (default 128) doing a read-modify-write refresh; a real write to the scrub address always wins over the stale scrub decode
- Saturating lifetime diagnostics n_ce/n_ue (corrected / uncorrectable event counts) that persist independently of the err_clear-able latched fault
- Any double-bit (uncorrectable) detection raises safety_monitor’s err_code = 1 (parity_mem, top priority), first-event-latched until err_clear
- No-vendor overlay: sized to replace XiangShan’s bit-sliced IntRegFilePart0..3/FpRegFilePart0..3 storage as one 64-bit-wide bank; the build references the integrator’s own XS_RTL checkout and never copies XiangShan RTL
Standards & Compliance
ISO 26262 ASIL-B SEooC (SPFM 92.10%, LFM 97.05%, PMHF 3.05×10⁻⁸/h)
Functional Safety
ASIL-B (SEooC) · SPFM 92.10% · LFM 97.05% · PASS
ISO 26262:2018 · FMEDA available · Safety Manual included
Register Map
See datasheet for full register reference.
Getting Started
// Minimal instantiation
xs_prf_ecc #(
.ADDR_W(6)
) u_xs_prf_ecc (
.clk (clk),
.rst_n (rst_n),
// APB4
.p_paddr (paddr),
.p_psel (psel),
.p_penable (penable),
.p_pwrite (pwrite),
.p_pwdata (pwdata),
.p_prdata (prdata),
.p_pready (pready),
// Safety
.err_clear (1'b0),
.err_valid (err_valid),
.err_code (err_code)
);
Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.
Applications
Where it fits
Typically deployed in RISC-V SoCs that need a safety-grade core, boot, memory, debug, and interrupt platform.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. FMEDA and Safety Manual available under NDA.