XiangShan Store-Queue Parity + Age-Order Overlay

What it is

xs_stq_parity is a safety overlay for the store queue (mem/lsqueue) of a XiangShan out-of-order RISC-V core: it shadows every committed-pending store’s {sequence age, address+data payload} with byte parity, and independently checks — via an expected-age counter — that entries drain to memory in the correct program order.

Key Features

• Byte parity over each entry’s age+payload, recomputed and compared at drain → drain_par_err → err_code 2 (data integrity)
• Independent expected-age (exp_age) monotonicity counter catches an out-of-order, parity-clean drain that data parity alone cannot see → drain_age_err → err_code 3 (order integrity)
• Saturating 32-bit event counters (n_par_err/n_age_err) that persist across err_clear — a lifetime diagnostic trend, independent of the latched fault
• Non-invasive shadow-array binding: driven by the real queue’s own allocate/drain indices, zero edits to vendored XiangShan RTL
• Overlay kit, never a vendored copy: build against your own XiangShan checkout (XS_RTL=…); this repo ships only the safety IP plus a referencing build
• Documents its own coverage boundary: the real queue’s store-to-load-forwarding (STLF) bypass read is NOT wired to a checked port by this RTL — an explicit integrator decision point, not a silent gap
• Feeds the shared safety_monitor, aggregated with xs_prf_ecc / xs_rob_parity / xs_iq_parity at xs_safety_island; FMEDA PASS ASIL-B (SPFM 93.88%, LFM 85.79%, PMHF 1.03×10⁻⁸/h, informational)

Standards & Compliance

ISO 26262 ASIL-B SEooC (informational, pre-sign-off — SPFM 93.88%, LFM 85.79%, PMHF 1.03×10⁻⁸/h); XiangShan open-source RV64GC OOO core (Mulan-PSL, no-vendor overlay kit)

Functional Safety

ASIL-B (SEooC) · SPFM 93.88% · LFM 85.79% · PASS

ISO 26262:2018 · FMEDA available · Safety Manual included

Register Map

See datasheet for full register reference.

Getting Started

// Minimal instantiation
xs_stq_parity #(
 .ADDR_W(6)
) u_xs_stq_parity (
 .clk (clk),
 .rst_n (rst_n),
 // APB4
 .p_paddr (paddr),
 .p_psel (psel),
 .p_penable (penable),
 .p_pwrite (pwrite),
 .p_pwdata (pwdata),
 .p_prdata (prdata),
 .p_pready (pready),
 // Safety
 .err_clear (1'b0),
 .err_valid (err_valid),
 .err_code (err_code)
);

Configure via the CTRL register after reset to enable the IP and set operating parameters. Monitor err_valid / err_code for any safety faults reported by the built-in safety monitor.