RISC-V Safety Subsystem

RISC-V ASIL Safety Island

A shrink-wrapped, ISO 26262-ready RISC-V safety subsystem.

Request the data room →All IP

FMEDA roll-up

The numbers that matter

SPFM — single-point fault metric99.42% · ASIL-D ≥ 99% ✓

LFM — latent-fault metric95.89% · ASIL-D ≥ 90% ✓

PMHF — probabilistic metric of HW failure9.26×10⁻⁹ /h · ASIL-D < 10⁻⁸ ✓

What’s inside

Architecture at a glance

A self-contained, lockstep-protected RISC-V compute + boot + isolation + fault-management island that drops into an SoC and arrives with the FMEDA work products already generated and a defensible Freedom-From-Interference argument closing a single-subsystem safety roll-up. You aren’t acquiring RTL — you’re acquiring ~12–18 months of certification schedule you get to skip.

Why now

There is no commercially shrink-wrapped, ISO 26262-ready RISC-V safety island on the open market. Arm answers this need with Cortex-R52 Split-Lock; the RISC-V ecosystem has a gap exactly this size. As automotive and industrial designs move to RISC-V, the first credible, FMEDA-backed safety island owns the on-ramp.

What’s in the box

Layer	Blocks
Safety compute	Dual-core lockstep (DCLS) RISC-V, RV32IMC
Boot / trust	SECDED boot ROM + bootloader, measured secure boot, lifecycle controller
Isolation (FFI)	Master-side access control — the freedom-from-interference enforcer
Timers / comms	RISC-V timer, multicore mailbox + spinlocks
Self-test (latent)	Logic-BIST + memory-BIST
Fault hub	Graded Low/High/Critical reaction to a single island safe-state
Clock/reset guard	Clock monitor, clock-domain crossing check, windowed watchdog, voter

100% built + integrated. One command brings up the island (bus decode, boot fetch, graded fault reaction); the subsystem roll-up and data room are packaged — the work is done, not new RTL.

The number that matters

A single subsystem FMEDA roll-up (failure-rate-weighted, ISO 26262-5) over the member IPs — the data-room metric no per-IP datasheet produces:

Metric	Achieved	ASIL-B	ASIL-D
SPFM	99.42 %	≥ 90 % ✅	≥ 99 % ✅
LFM	95.89 %	≥ 60 % ✅	≥ 90 % ✅
PMHF	9.26 × 10⁻⁹ /h	< 10⁻⁷ ✅	< 10⁻⁸ ✅

Today: meets all three ASIL-D targets. The roll-up’s PMHF is licensed by a written Dependent-Failure Analysis (ISO 26262-9): spatial isolation, temporal independence, and a common graded safe-state. This is a pre-sign-off engineering roll-up — the safety-critical lockstep core is fault-injection-measured; the supporting tier is estimate-grade pending silicon.

Full FMEDA roll-up, DFA, and RTL data room under mutual NDA.Request the data room →

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space

Proof

Real silicon flow — inspect it under NDA

Subsystem FMEDA roll-up — SPFM / LFM / PMHF

Bring RISC-V ASIL Safety Island into your program

Full FMEDA, DFA/formal proofs, and the RTL data room follow under a mutual NDA.

Request the data room →Browse the catalog

Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. “ISO 26262-ready” means the work products are generated — not that the IP is third-party certified.

circuit-design.space · +1-971-357-1400 · sales@circuit-design.space