A self-contained coherent CHI fabric — caching agents (RN-F) sharing one Home Node point-of- coherency over an interconnect, terminated in a real LPDDR5 controller, with in-system trace and latency observability — that drops into an SoC with the FMEDA work products already generated, coherency proven by formal, and data-value coherence demonstrated end-to-end onto real LPDDR5. You’re not acquiring RTL — you’re acquiring a coherent fabric whose safety and correctness case is already assembled.
Coherent fabrics are the backbone of multi-core SoCs, and AMBA-5 CHI is the interconnect the industry standardized on — but a safety-instrumented, formally-verified CHI subsystem that comes with its FMEDA and a real memory endpoint is not something you can buy off a shelf.
| Element | Function |
|---|---|
| Caching agents (RN-F) | Fully-coherent requesters sharing state |
| Home Node (HN-F) | The point-of-coherency — orders and resolves |
| Interconnect | CHI channel fabric between agents and home |
| LPDDR5 controller | Real DRAM endpoint — coherence demonstrated onto silicon-class memory |
| Observability | In-system trace + latency monitoring |
Full formal proofs, FMEDA, and RTL data room under mutual NDA.Request the data room →
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space
Full FMEDA, DFA/formal proofs, and the RTL data room follow under a mutual NDA.
Figures are pre-silicon engineering-grade estimates for a Safety Element out of Context (SEooC); final ASIL sign-off is the integrator’s, supported under NDA. “ISO 26262-ready” means the work products are generated — not that the IP is third-party certified.
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space