Line rate is not throughput. This subtracts both taxes — the line coding fixed by the standard, and the protocol framing set by your transfer size — to give the payload bandwidth your application actually sees, for PCIe, CXL, Ethernet, USB, CAN and the rest.
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A bus advertises a line rate. What your application receives is that rate after two separate deductions, and only the first is widely known.
Line coding is the physical-layer tax, and it is fixed by the standard. 8b/10b sends ten bits for every eight, so a fifth of the wire carries no data at all — that is why SATA III's 6 Gbps is exactly 600 MB/s and never more. Modern SerDes standards moved to 128b/130b or 64b/66b precisely to stop paying it, dropping the cost from 20 % to about 1.5 %. This term is exact and non-negotiable.
Protocol framing is the tax people forget, and it depends on how you use the link rather than on the link itself. Every transfer carries headers, sequence numbers, CRCs and gaps, and those are amortised over the payload you put behind them. Move 4096-byte blocks and it disappears into the noise. Move 64-byte cache lines and it can cost more than the line coding did. That is why payload size is an input here and not a constant.
| Link | Line rate | Real payload | What happened |
|---|---|---|---|
| PCIe Gen4 x16 | 256 Gbps | ~29 GB/s each way | 128b/130b costs 1.5 %, TLP framing at 256 B costs another 8 %. |
| SATA III | 6 Gbps | ~576 MB/s | 8b/10b alone removes 1.2 Gbps. The ceiling that killed SATA SSDs. |
| 10 GbE, 1500 B frames | 10 Gbps | ~9.4 Gbps | 64b/66b plus 38 bytes of wire slot per frame. |
| 10 GbE, minimum frames (46 B payload) | 10 Gbps | ~5.3 Gbps | Same link, same coding. The payload just got too small to amortise the gap. |
| Classic CAN, 8 B | 1 Mbps | ~504 kbps | Arbitration, CRC, ACK and worst-case stuffing take just under half the bus. This is why CAN FD exists. |
The two Ethernet rows are the same hardware. Nothing changed but the frame size, and half the link evaporated. Small-packet forwarding at line rate is a genuinely hard problem for this reason, and it is why switch datasheets quote packets per second alongside bits per second.
PCIe, Ethernet and AXI are full duplex: separate paths each way, so the aggregate really is twice one direction. Vendors quote that aggregate because it is the larger number. It only helps you if your traffic is genuinely bidirectional — a DMA read that streams one way uses half of it and no more. USB 2.0, SATA, CAN, SPI and I2C are half duplex or shared, so there is no doubling to quote, and on USB 2.0 the bandwidth is shared across every device on the controller as well.
Worth selecting both and comparing, because it is counter-intuitive. CXL uses the identical PCIe electrical layer — same rate, same coding — yet its effective throughput is lower. Nothing is wrong with CXL: the difference is that CXL.mem moves 64-byte cache lines while a PCIe device doing bulk DMA moves 256-byte or larger TLPs, so the same fixed framing overhead is spread over a quarter as much payload. The link did not change; the transfer size did. It is the clearest illustration on this page that the second tax is about your traffic, not your wire.
Link-layer retries, flow-control credit starvation, encryption overhead, and the fact that a real controller may simply not be able to keep the link busy. Every figure here is an upper bound on payload throughput given perfect scheduling; if you measure less, the gap is your controller, your DMA engine or your software, not the standard. It also treats the link as error-free — a marginal channel that is retrying is a signal-integrity problem wearing a bandwidth costume, and the BER and jitter and channel loss tools are where that gets diagnosed.
If the far end of the link is memory rather than a peer, the memory bandwidth calculator does the same subtraction for DDR, LPDDR, GDDR and HBM — where the overheads are refresh, bus turnaround and row misses rather than line coding and framing. For the physical layer that has to carry these rates, impedance, crosstalk and pair skew are the constraints that decide whether the link runs at all.
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