Microstrip, stripline and edge-coupled differential, with presets for common laminates. Beyond the single number, it plots impedance against whichever variable you are free to change — width, separation or dielectric height — and works out what your fabricator’s tolerances actually cost you in ohms.
| Sensitivity | Ω per unit | Over a typical tolerance | What that means |
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Every impedance calculator returns a single value for a single geometry. That answers the wrong question. On a real board you are not choosing a geometry from nothing — you are asking how much room you have, which variable to move, and whether your fabricator can hold what you just specified.
So this one plots impedance against the variable you are free to change, marks your current design point on the curve, and draws your target across it. A glance tells you whether you are on a steep part of the curve, where a mil of etch matters, or a flat part where it does not.
A nominal 50 Ω is worth very little if the manufacturing spread is ±8 Ω. The table converts each geometry variable into ohms per unit and then into what a realistic tolerance actually costs:
The three are stacked in quadrature into a single expected spread. Compare that against the ±10% your fabricator will quote: if your stacked tolerance is already ±9%, the nominal being 1% off is not your problem, and asking for ±5% impedance control on that stackup is asking to pay for coupons and yield loss.
Zmicrostrip = 87/√(Dk+1.41) · ln( 5.98h / (0.8w + t) )Zstripline = 60/√Dk · ln( 4b / (0.67π(0.8w + t)) )Zdiff = 2Z0(1 − 0.48 e−0.96 s/h) microstrip,
2Z0(1 − 0.347 e−2.9 s/b) stripline
These are the IPC-2141 approximations, and they are genuinely useful inside their range: roughly 0.1 < w/h < 3 for microstrip and w/b < 0.35 for stripline. Outside it they drift, sometimes badly. The tool tells you when you have left the valid range instead of returning a confident wrong answer, which is more than most calculators do.
Coupling matters. Two 50 Ω traces placed near each other do not give 100 Ω differential — they give less, because each trace's field interacts with its neighbour. The exponential terms above capture that, and they show the useful behaviour: coupling falls off fast with separation, so beyond roughly three times the dielectric height the pair is effectively uncoupled and moving them further apart changes almost nothing.
Switch the sweep to separation and you can see exactly where that knee is for your stackup. It is usually much closer than people route to, which means the space spent on wide pair separation is often free to reclaim.
A microstrip has field lines partly in the laminate and partly in air, so it sees an effective Dk lower than the material's own — and it propagates faster than a stripline on the same board, typically 140–150 ps/inch against 170–180. The tool reports both. That difference matters for length matching whenever a net changes layers, and it is covered in the differential pair skew calculator.
Signal and power integrity is one of our primary service lines, and stackup and impedance planning is where it starts — before routing, when width, spacing and layer assignment are all still free. A pre-layout constraint study settles all of it in one to two weeks; post-layout we verify against the real geometry in Ansys SIwave and Siemens HyperLynx. The related channel loss budget and via stub tools cover the other two things that decide whether a high-speed link works.
Each of these runs entirely in your browser. Nothing is uploaded, stored or sent anywhere, and none of them needs an email address.
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