Free tool

MCU / SoC Family Selector

Answer the questions an experienced engineer would ask you, and get a shortlist of families worth evaluating — plus, more usefully, every family that was ruled out and the single constraint that did it. 35 families surveyed, at family granularity, from a dataset kept separately so it can be corrected as it ages.

Runs entirely in your browser. Nothing is uploaded, stored, or sent anywhere.

What this is, and what it deliberately is not

There are several thousand microcontroller and SoC part numbers in production, and no selection tool can pick one for you honestly. What it can do is get you from every family on the market down to the five or six worth an afternoon each, and tell you exactly why it discarded the rest — which is the more useful half, because the reasons are where you discover that one of your requirements is the expensive one.

So this works at family granularity, never at part granularity. When it says a family offers CAN-FD and PCIe, that means parts in the family commonly offer those; it does not promise a single part offers both. Once you have a shortlist, the vendor's own parametric search is what picks the part, and nothing here substitutes for it.

The rejections are the interesting output

The table of ruled-out families is sorted so that anything eliminated by a single constraint appears first. Those are the near misses, and they usually prompt the most productive conversation on a project: a family that fails only on temperature grade might have an automotive variant; one that fails only on longevity might be fine if the product is a three-year consumer device; one that fails only on Linux capability might work perfectly if the display could move to a separate module.

If nothing survives, that is a real result too, and almost always means two requirements are fighting. ASIL-D with Linux on one chip, a coin-cell power budget with Ethernet, or 150 °C with an edge-AI NPU are all combinations that push you towards splitting the design across two devices — which is what the empty result is telling you.

Where the survey data comes from, and how wrong it will be

The dataset behind this tool is kept as a separate, versioned artifact rather than being buried in the page, with its own provenance notes, per-family confidence marks and an explicit list of its own limitations. That is deliberate: a dataset this size will be wrong somewhere and will go stale everywhere, and it should be correctable without touching the tool that reads it.

Entries marked medium confidence are ones where the family is broad or moving quickly — new parts add PCIe, TSN or an NPU, and older ones quietly move to not-recommended-for-new-design. Treat those as prompts to check rather than as facts. The figures throughout are bands and typical family characteristics, not datasheet values for a specific device.

Two things this cannot see, and they decide many projects. The first is what your team already knows: an unfamiliar architecture costs months, and a "better" part that nobody has used before frequently loses to a worse one with an existing BSP, a working toolchain and colleagues who have debugged it. The second is supply. A family with a fifteen-year longevity commitment and a family with none can look identical in a specification table and be completely different risks for a product that has to ship for a decade.

A note on functional safety entries

Where a family is marked ASIL-D or SIL3, that means the vendor offers a safety package — a safety manual, an FMEDA, a safety element out of context, and usually a certified compiler and diagnostic library. It does not mean the device is "ASIL-D" on its own, because no component is: the integrity level belongs to your item, and the silicon is one input to that argument. Choosing a part with a mature safety package saves a great deal of work, but it does not remove the obligation to do the FMEDA on your design.

If that is the road you are on, the ASIL determination calculator establishes the target, FIT and PMHF shows what each element has to reach, the safety mechanism selector covers what to put around the parts that cannot reach it alone, and decomposition is the lever when a single device cannot carry the goal. If the shortlist has pushed you towards an external DRAM interface or a high-speed serial link, the memory bandwidth and bus bandwidth calculators size those, and the stackup planner turns the resulting BGA into a board.

More free tools

Each of these runs entirely in your browser. Nothing is uploaded, stored or sent anywhere, and none of them needs an email address.

Memory bandwidth + latency →
DDR, LPDDR, GDDR and HBM after refresh, turnaround and row misses — not the headline figure.
Bus bandwidth after overhead →
PCIe, CXL, Ethernet, USB, CAN — line rate minus line coding and protocol framing.
ASIL determination →
Severity, exposure and controllability to an ASIL, with the reasoning shown.
FIT & PMHF budget →
Failure rate and diagnostic coverage to SPFM, LFM and PMHF for one element.

See all 49 engineering tools →

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