Give it the BGA pitch, the interfaces on the board and the fabricator, and it works the chain forwards: how many layers the escape actually needs, which laminate the fastest signal demands, the full core and prepreg construction to your finished thickness, the drill aspect ratio, and the trace width for every impedance target on every signal layer.
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Most stackup references show you a picture of an eight-layer board. That is not the hard part. The hard part is that the layer count, the material, the dielectric heights, the trace widths and the via technology are all coupled — change the BGA pitch and the layer count moves; change the layer count and every dielectric height moves; change those and every trace width moves; and if the board got thicker, the drill aspect ratio may have gone out of range.
This tool works that chain forwards. You give it the package, the interfaces and the fabricator, and it derives the rest.
The number of layers a board needs is usually set by one question: how many BGA rows can you bring out per routing layer? That follows from geometry you can compute. Subtract the via land from the ball pitch and you have the channel between adjacent vias. Take the clearance off each side and see how many traces fit. Each routing layer then escapes the row it terminates on, plus one row for every trace that fits through the channel.
At 1.0 mm pitch with ordinary rules, two traces fit and each layer brings out three rows. At 0.8 mm with the same rules, often one trace fits, so each layer brings out two. At 0.65 mm, frequently none fits — each layer escapes exactly one row, and the layer count doubles. That single step is why a 0.65 mm part can cost twice as much to route as a 0.8 mm one with the same ball count, and it is worth knowing at package-selection time rather than at layout time.
Below 0.5 mm the question stops being how many traces fit between the lands, because a through-via land does not fit in the channel at all. That is the HDI boundary: via-in-pad with microvias, sequential lamination, and a different cost structure.
Laminate selection is driven by loss, and loss is driven by the dissipation factor. Standard FR-4 at Df 0.02 is entirely adequate below a couple of gigabits and hopeless at sixteen. The tool picks a class from the fastest interface you selected and names representative laminates for it.
What the class alone does not tell you is the glass style, which at high rates matters just as much. Standard 7628 glass is a coarse weave, and a differential pair whose two traces happen to sit over resin and over glass bundle respectively will see different effective Dk and accumulate skew along the length. Above about 10 Gbps that skew becomes a real budget item, and the fixes are spread glass, a flatter style such as 1078 or 3313, or routing a few degrees off the weave axis. Our differential pair skew calculator quantifies what it costs you.
The stack this tool builds gives the outer dielectric layers a smaller share of the total thickness than the inner ones. That is not arbitrary. Outer-layer traces are microstrips referenced to the plane immediately below, and the impedance depends on the ratio of dielectric height to trace width. Give the outer prepreg an equal share of a 1.6 mm board and a 50 Ω microstrip needs an implausibly wide trace — wide enough that it will not fit in a BGA escape channel, which defeats the point. Thin outer dielectric, narrow controlled-impedance traces, and the escape still works.
Drill aspect ratio is board thickness divided by the smallest finished hole. Plating chemistry has to throw all the way down that hole and produce an even wall, and beyond roughly 10:1 the yield falls away. It belongs on this page because it couples straight back into the stackup: a thick board with fine drills is exactly the combination a dense BGA pushes you towards, and when it goes out of range your options are a thinner board, a larger minimum drill, or blind and buried vias. For microvias the ratio is defined differently — depth over diameter, wanting to stay near 0.75:1 — which is one of the constraints that sets the outer dielectric thickness on an HDI board. The DFM checker covers the rest of the manufacturability envelope: annular ring, drill-to-copper and the capability band each parameter lands in.
The widths here come from the IPC-2141 closed-form approximations, the same ones our trace impedance calculator uses — deliberately, so the two tools cannot disagree about the same geometry. They are good to a few percent over the usual range of w/h, and they are not a field solver. They ignore soldermask over the microstrip (which pulls impedance down a few ohms), copper roughness, etch taper — the trapezoidal cross section a real etched trace has rather than the rectangle the formula assumes — and resin-content variation between prepreg constructions.
Use these to size the stack and to know whether a target is reachable at all. Before release, send the intended construction to the fabricator and have them run their field solver and return a stackup drawing with their own widths on it. They will adjust, and they will be right, because they know their glass styles and press cycle. Where this tool earns its keep is the twenty iterations before that point.
Once the stack exists, the loss and timing questions follow: the channel loss calculator tells you how far the chosen laminate will carry the fastest interface, crosstalk sets the spacing between adjacent pairs, and via stub resonance decides whether the through-vias need backdrilling.
Each of these runs entirely in your browser. Nothing is uploaded, stored or sent anywhere, and none of them needs an email address.
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