← All Verification IPAMBA / On-Chip Bus
ACE4 / ACE4-Lite
AXI-Coherency-Extension verification (cache-maintenance and barrier transactions, speculative read…
plannedGroup AMBA / On-Chip BusStandard ARM AMBA 4 ACE
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
AXI-Coherency-Extension verification (cache-maintenance and barrier transactions, speculative read, the optional Snoop-Data CD channel) for designs that bridge into this catalog’s CHI-side coherency fabric from an ACE-speaking cluster.
Key Features
- Cache-maintenance operation (CMO) and barrier-transaction sequencing
- Speculative-read generation with early/late completion timing
- Optional Snoop-Data (CD) channel modeling for cache-to-cache transfers
- Coherent / non-coherent (ACE-Lite) mode split for mixed-cluster topologies
Standards & Compliance
ARM AMBA 4 ACE
Interested in the ACE4 / ACE4-Lite VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space