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64b/66b
Standalone 64b/66b line-coding verification — the higher-efficiency successor to 8b/10b used by 10GbE-and-above Ethernet and PCIe Gen3, reusable under the Ethernet and PCIe VIPs.
plannedGroup Cores / On-Chip Infra / MiscStandard IEEE 802.3 64b/66b line coding (10GbE+, PCIe Gen3)
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Standalone 64b/66b line-coding verification — the higher-efficiency successor to 8b/10b used by 10GbE-and-above Ethernet and PCIe Gen3, reusable under the Ethernet and PCIe VIPs.
Key Features
- Encode/decode verification with scrambler/descrambler polynomial checks
- Sync-header (01/10) framing and block-lock acquisition scenarios
Standards & Compliance
IEEE 802.3 64b/66b line coding (10GbE+, PCIe Gen3)
Interested in the 64b/66b VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
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