← All Verification IPCores / On-Chip Infra / Misc
8b/10b
Standalone 8b/10b line-coding verification — encode/decode, running-disparity control, and comma/K-character alignment, reusable underneath several of the catalog’s SerDes-layer VIPs.
plannedGroup Cores / On-Chip Infra / MiscStandard IBM 8b/10b line coding (widely reused: PCIe Gen1/2, SATA, Fibre Channel, GbE)
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Standalone 8b/10b line-coding verification — encode/decode, running-disparity control, and comma/K-character alignment, reusable underneath several of the catalog’s SerDes-layer VIPs.
Key Features
- Encode/decode verification with running-disparity control
- Comma/K-character detection and byte/lane alignment scenarios
Standards & Compliance
IBM 8b/10b line coding (widely reused: PCIe Gen1/2, SATA, Fibre Channel, GbE)
Interested in the 8b/10b VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space