AHB5 / AHB3-Lite

An independent AHB-Lite master, written clean-room from the public AHB-Lite address/data-phase handshake contract — not derived from our own ahb_to_tl_ul RTL — so it functions as a true second source. Since no real TL-UL target IP exists yet in this catalog, a small independent TL-UL memory-model responder completes the loop on the bridge’s far side so end-to-end write/read-back transactions can actually finish. Ships with a passive protocol checker (single-outstanding handshake legality, no-SEQ, HRESP-phase legality) and a self-checking interop TB proving word and sub-word (byte/halfword) writes, read-back, the TL-denied→HRESP=ERROR path, and TL-side wait-state stalling against the catalog’s ahb_to_tl_ul bridge. Covers only single, non-pipelined NONSEQ transfers — matching the bridge’s own documented single-outstanding, no-SEQ/burst scope — burst/SEQ transfers and pipelined back-to-back address phases are a documented roadmap item, not yet built.

Key Features

• Independent AHB-Lite master: WRITE/READ + sub-word WRITE_BYTE/WRITE_HALF task API
• Independent TL-UL memory-model responder standing in for the (not-yet-shipping) TL-UL target, with configurable wait-state and TL-denied injection
• Passive AHB-Lite protocol checker: single-outstanding handshake legality, no-SEQ, HRESP-phase legality — never reading DUT-internal state
• Self-checking interop TB against the catalog’s ahb_to_tl_ul: word/sub-word writes, read-back, TL-denied error path, wait-state stalling, plus a directed injection caught by the checker

Standards & Compliance

ARM AMBA 5 AHB / AMBA 3 AHB-Lite

Pairs With

Built to lean against these catalog IPs during integration:

• ahb_to_tl_ul
• tl_ul_to_ahb