CXL.mem (transaction layer)

An independent clean-room CXL.mem VIP, and this one is DUT INTEROP rather than a BFM self-check: ip/cxl_mem_dev is a real Type-3 memory expander in this catalog, so the host root drives the actual RTL and an independently written memory model sits behind its downstream line port (“cxl/, make cxl_oss, 30/30 checks). Covers all four CXL.mem channels (M2S Req / M2S RwD / S2M DRS / S2M NDR), credited S2M flow control, HDM address decode, end-to-end SECDED through the real device (single-bit corrected and counted, double-bit poisoned), downstream bus errors, and the CXL 3.0 back-invalidate pair. Six rules, each pinned by a per-rule mask to its own injected fault. SCOPE: the transaction layer down to the flit boundary. CXL.io and the PCIe link and PHY beneath it are vip-pcie’s and are out of the device’s own scope too; .cache is not modelled, and neither is the multi-device switching that vip-cxl-switch would cover. It found a real defect in the device on its first run: a BISnpInv answered BIRspS — “I kept a shared copy”, which does not satisfy an invalidate — was accepted as completion, and a bias-flip back-invalidate would take Device Bias on it. And its sharpest test is a NEGATIVE one: a DRS flit carries data AND a poison bit, and honouring poison is entirely internal to the receiver. Two hosts fed the identical flit disagree about whether a line the device could not correct becomes live data; every rule passes and the checker is silent.

Key Features

• DUT interop against the real ip/cxl_mem_dev, not a BFM-against-BFM self-check
• All four CXL.mem channels with credited S2M flow control and HDM decode
• End-to-end SECDED exercised through the device: SBE corrected + counted, DBE poisoned
• CXL 3.0 back-invalidate (S2M BISnp / M2S BIRsp) including response-opcode checking
• Passive checker, 6 rules, each pinned by a per-rule mask to its own injected fault
• The poison-honouring blind spot named and asserted, not papered over

Standards & Compliance

Compute Express Link (CXL) — CXL.mem transaction layer, incl. CXL 3.0 back-invalidate

Pairs With

Built to lean against these catalog IPs during integration:

• cxl_mem_dev
• pcie_tl_bridge
• ddr5_ctrl