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HBM3E/3/2
Stacked-die High Bandwidth Memory verification across three shipping HBM generations — wide-parallel channel command/data and per-channel independent refresh.
plannedGroup MemoryStandard JEDEC HBM3E / HBM3 / HBM2 (JESD238/JESD235)
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Stacked-die High Bandwidth Memory verification across three shipping HBM generations — wide-parallel channel command/data and per-channel independent refresh.
Key Features
- Wide-parallel (1024-bit-class) channel command/data verification
- Per-channel independent refresh and pseudo-channel-mode scenarios (HBM2E+)
- Built-in self-test (BIST) and repair-mode command sequencing
Standards & Compliance
JEDEC HBM3E / HBM3 / HBM2 (JESD238/JESD235)
Interested in the HBM3E/3/2 VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
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