Memory

LPDDR5 / 5X

Mobile DRAM interface verification directly against the catalog’s own LPDDR5/DFI controller — DFI transport, per-bank refresh, and RAS-layer scenarios.

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plannedGroup MemoryStandard JEDEC LPDDR5 / LPDDR5X (JESD209-5)

Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What is scoped

Scoped, not yet built

This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.

Ask if you need it sooner

Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.

Same shape when it lands

Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.

Mobile DRAM interface verification directly against the catalog’s own LPDDR5/DFI controller — DFI transport, per-bank refresh, and RAS-layer scenarios.

Key Features

DFI transport-layer command/data sequencing against a DFI-compliant controller
Per-bank refresh and RAS-layer (Row Activation Steering) scenarios
Dynamic frequency/voltage-scaling (DVFSC) mode-switch verification

Standards & Compliance

JEDEC LPDDR5 / LPDDR5X (JESD209-5)

Pairs With

Built to lean against these catalog IPs during integration:

lpddr5_ctrl

Interested in the LPDDR5 / 5X VIP?

This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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