LVDS

An independent clean-room LVDS display-link VIP: a transmitter BFM that packs a pixel into 4 lanes × 7 slots, a separately written receiver BFM that unpacks it using ITS OWN configured convention, and a passive checker (“lvds/, make lvds_oss, 22/22 checks). It covers both bit-mapping conventions (VESA/SPWG and JEIDA) in RGB888 and RGB666, clock-lane framing, and DE/HS/VS placement — with a walking-ones test that proves the packer/unpacker pair is a bijection over all 24 colour bits, so a single transposed slot cannot hide behind a pixel ramp. SCOPE: digital framing and bit mapping only. The ANSI/TIA/EIA-644 electrical layer (differential levels, common mode, termination, skew) is NOT modelled and needs an analog/AMS flow; dual-channel odd/even pixel splitting is not modelled either. The VIP’s sharpest result is a NEGATIVE one: a VESA transmitter feeding a JEIDA-strapped receiver produces a perfectly legal wire — same framing, same clock pattern, same sync placement, same 28 slots — so no passive monitor can see it, and the receiver reports a healthy link while showing the wrong colours. That is the most common LVDS bring-up fault in the field, and T7 asserts BOTH halves: the checker stays silent AND the pixels come back wrong.

Key Features

• 7:1 pixel-to-serial mapping, RGB888 (4 lanes) and RGB666 (3 lanes), + HS/VS/DE
• VESA/SPWG and JEIDA bit mapping, both proven bijective by a walking-ones test
• Passive checker: clock-lane framing, lane-3 idle on a 3-lane link, DE-inside-sync
• Injected faults: corrupt clock pattern, DE in a sync pulse, lane 3 driven in RGB666
• The mapping-mismatch blind spot named and asserted, not papered over

Standards & Compliance

JEIDA / VESA (SPWG) LVDS display mapping, 7:1 pixel serialization