Storage

NVMe 2.0/1.4 (queue protocol)

An independent clean-room NVM Express queue-protocol VIP: a controller that fetches Submission Queue Entries and completes them out of order…

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shippingGroup StorageStandard NVM Express Base Specification 2.0 / 1.4 — queue protocol

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent clean-room NVM Express queue-protocol VIP: a controller that fetches Submission Queue Entries and completes them out of order, a separately written host driver model that reaps by PHASE TAG and keeps its own mirror of the phase, and a passive queue checker (“nvme/, make nvme_oss, 25/25 checks). Covers Submission and Completion Queue pairs, head and tail pointers, doorbells, the phase tag, Command Identifiers, out-of-order completion, and the SQ-head-pointer feedback a controller uses for back-pressure. Six rules, each pinned by a per-rule mask to its own injected fault. It also encodes a real decoder trap: admin opcode 0x01 is Create I/O SQ and NVM opcode 0x01 is Write, so the queue must be decoded before the opcode — R1 is written queue-first on purpose. SCOPE: the queue protocol. PCIe underneath is vip-pcie (which models the wire), NVM command semantics are an opaque opcode, and namespaces, PRPs/SGLs and data transfer are out. The sharpest result is a NEGATIVE one: a Command Identifier names a SLOT, not a command, and is reusable the moment its command completes. A completion re-posted after the CID has been handed on passes the outstanding-CID rule (the CID IS outstanding) and the duplicate-CID rule (the previous holder DID complete first). Every field is legal, and one command’s status is attributed to another.

Key Features

Submission/Completion queue pairs, circular head and tail pointers, doorbells
Phase tag as the sole validity mechanism, mirrored independently at both ends
Out-of-order completion by Command Identifier, each status attributed correctly
SQ head-pointer back-pressure feedback carried in every completion
Passive checker, 6 rules, each pinned by a per-rule mask; R1 decodes queue-before-opcode
The stale-completion-on-a-reused-CID blind spot named and asserted, not papered over

Standards & Compliance

NVM Express Base Specification 2.0 / 1.4 — queue protocol

Pairs With

Built to lean against these catalog IPs during integration:

pcie_tl_bridge

Interested in the NVMe 2.0/1.4 (queue protocol) VIP?

Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space