Serial & Control Bus

UART / USART

An independent UART transceiver, written clean-room from the generic async-serial framing convention — not derived from our own uart RTL — so it functions as a true second source.

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shippingGroup Serial & Control BusStandard Modeled on the National Semiconductor PC16550D UART/USART

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model

An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.

Passive protocol checker

A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.

Self-checking interop testbench

A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent UART transceiver, written clean-room from the generic async-serial framing convention — not derived from our own uart RTL — so it functions as a true second source. Ships with a passive protocol checker that verifies stop-bit framing on a timed 8N1 grid independently of either side’s internal state, and a self-checking interop TB proving both directions (RX into the catalog uart, TX out of it) against the real 16550-compatible register interface, including baud-divisor configuration via DLAB. Covers 8N1 framing only (8 data bits, no parity, 1 stop bit — also uart‘s own reset default) — parity and word-length/stop-bit variants are a documented roadmap item, not yet built. Building the interop TB also surfaced a same-clock-edge simulation race in how a destructive (FIFO-draining) register read must be sampled in a testbench — fixed in the TB, not the DUT.

Key Features

Independent 8N1 transceiver: SEND/RECV task API + a SEND_BAD_STOP error-injection primitive
Passive protocol checker: stop-bit-cell-must-be-HIGH framing legality on a timed bit grid
Self-checking interop TB against the catalog’s uart: RBR (RX) path, THR (TX) path, and baud-divisor (DLAB/DLL/DLH) configuration — all pass
Scope today is 8N1 only; parity and 5/6/7-bit word-length / 1.5/2 stop-bit variants are roadmap, not yet built

Standards & Compliance

Modeled on the National Semiconductor PC16550D UART/USART

Pairs With

Built to lean against these catalog IPs during integration:

uart

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Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

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