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xHCI (ring protocol)

An independent clean-room xHCI ring-protocol VIP: a host controller that consumes TRBs by cycle bit and posts events…

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shippingGroup USBStandard Intel eXtensible Host Controller Interface (xHCI) Specification

Available now — real, tested verification collateral, not a roadmap placeholder.

Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.

The deliverable

What you get

Bus-functional model
An independent driver for the protocol, written clean-room from the public specification — not derived from our own RTL, so it is a genuine second source.
Passive protocol checker
A monitor that watches the bus and asserts the spec’s rules continuously, so a violation fails the run where it happens rather than downstream.
Self-checking interop testbench
A one-command testbench that drives the model against real RTL and hard-checks the result — reproduce every claim on day one.

An independent clean-room xHCI ring-protocol VIP: a host controller that consumes TRBs by cycle bit and posts events, a separately written software driver model that maintains its own producer cycle state and retires events with the ERDP, and a passive ring checker (“xhci/, make xhci_oss, 24/24 checks). Covers the 16-byte Transfer Request Block, Command and Event rings as circular TRB arrays, the CYCLE BIT that makes a ring self-describing, Link TRBs with Toggle Cycle, doorbells, the Event Ring Dequeue Pointer, completion codes and residual lengths. Six rules, each pinned by a per-rule mask to its own injected fault. SCOPE: the ring protocol. The full register map, DMA and scatter-gather, slot and endpoint contexts and bandwidth management are NOT modelled, and “memory” is a write channel from software to the controller rather than a fabric — enough to model who wrote what and in which order, and honest about not being a DMA model. The sharpest result is a NEGATIVE one. A Transfer Event’s length field carries the RESIDUAL — the bytes NOT transferred — so on a completed full-length transfer it reads zero. T9 feeds the same bit-identical event to two drivers that differ only in how they read that field: one concludes 512 bytes moved, the other concludes none did. Both consume the event and write the same ERDP, so the checker is blind by construction. The field is right there on the interface and the checker reads it — what it cannot read is what the number MEANS.

Key Features

Standards & Compliance

Intel eXtensible Host Controller Interface (xHCI) Specification

Pairs With

Built to lean against these catalog IPs during integration:

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Deliverables, the file manifest, and licensing terms are shared under a mutual NDA.

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Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.

circuit-design.space · +1-971-357-1400 · anovickis@circuit-design.space