Enter the rail voltage, the ripple you can tolerate and the transient current step. The calculator returns the target impedance, how many decoupling capacitors it takes to hold it, and the bulk capacitance the low end needs.
| Capacitor type | Value (µF) | Mounted ESL (nH) | ESR (mΩ) | Qty | Self-resonance | Bank Z at SRF |
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A power delivery network has one job: keep the rail inside its tolerance while the load changes. If the load can step by ΔI and the rail may only move by ΔV, then the network has to present an impedance below ΔV/ΔI — at every frequency the load can excite, not just at DC.
ΔV = Vrail × ripple ·
Ztarget = ΔV / ΔIZbank,i(f) = ESRi/ni + j( 2πf·ESLi/ni − 1/(2πf·niCi) )Zload(f) = 1 / Σ(1/Zbank,i) + Rpath + j·2πf·LpathThe three banks are combined as complex admittances, then the path is added in series, because that is where it physically sits: between the capacitors and the die. The tool sweeps the whole band and reports the worst case rather than a single spot frequency.
The two ends of the range are limited by different things. At the low end you need charge: enough capacitance that its reactance is still under the target near the VRM crossover. At the high end you need low inductance: capacitors in parallel divide their mounted inductance, so the count there is set by inductance and not by capacitance at all.
No single part does both. A 100 µF bulk capacitor has the charge and far too much inductance; a 0.1 µF part has the inductance and nowhere near the charge. That is why real designs carry three decades of capacitance, and it is why this tool asks for three types and gives you a count for each. Suggest counts sizes them the way the physics divides the problem — bulk from the low-frequency charge requirement, high-frequency from the inductance budget at the top of the band, and the mid-band part bridging at the geometric mean of the two outer self-resonances.
Capacitors do not connect to the load; they connect to a plane, which connects through vias to a package, which connects to the die. That path has resistance and inductance of its own, and it is in series with everything the capacitors do. Parallelling more capacitors divides the bank's inductance and does nothing whatsoever to the path's.
So there is a hard ceiling. Above the frequency where the path inductance alone reaches the target, no capacitor count on the board can help — the parts are on the wrong side of that inductance. The tool computes that ceiling from your numbers and says so plainly when your fmax sits above it. With the defaults it lands around 160 MHz; drop the path from 5 pH to 50 pH and watch it fall by a factor of ten while the capacitor count changes nothing. This is the single most common reason a PDN that calculated fine measures badly, and it is a layout outcome, not a BOM one.
The same applies to the resistance: if the path resistance alone exceeds the target, that is a DC problem, and no amount of decoupling addresses a DC drop.
Signal and power integrity is one of our primary service lines — pre-layout constraint development through post-layout verification in Ansys SIwave and Siemens HyperLynx, including the anti-resonance behaviour this estimate deliberately cannot show. A PDN and decoupling review runs about a week to a fixed scope, and a pre-layout constraint study one to two weeks. Both end in a written report you keep.
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