Give it the job and it lets every surveyed regulator try: 154 regulators from 41 vendors, each designed end to end with a real inductor, real switches and a DC-bias-derated capacitor bank, then ranked by cost, efficiency, size or noise. You get a schematic, a bill of materials with datasheet links, loop gain and output-impedance plots, efficiency against load, the enable, delay and soft-start parts — and every part that was ruled out, with the reason.
Runs entirely in your browser. Nothing is uploaded, stored or sent anywhere. Part survey last updated 2026-09-29: 154 regulators (34 from mainland-China vendors, shown only if you opt in), 26 inductor series, 21 MOSFETs and 11 Schottky diodes.
Every regulator vendor has a design tool, and every one of them starts from the assumption that you have already chosen their part. This one starts one step earlier. It takes the job — input range, output, load, what you are optimising for — and lets every surveyed regulator from every vendor try to do it, including the topologies you did not ask about. Each survivor is designed completely: frequency, inductor, capacitor banks, switches, divider, compensation targets, losses, temperature and area. Then they are ranked, and the ones that failed are listed with the constraint that killed them.
The rejected list is the half worth reading. A part that fails only on minimum on-time at your maximum input voltage is telling you the frequency window is too high for that conversion ratio; a part that fails only on junction temperature is telling you that your ambient, not the silicon, is the problem; and an empty shortlist almost always means two requirements are fighting — very low noise and a large step-down, say, which is what the two-stage suggestion is for.
In the default mode the topologies compete rather than being picked by rule. A buck is tried whenever the lowest input sits comfortably above the output, an LDO whenever there is any headroom at all, and a boost whenever the highest input sits below the output. SEPIC and four-switch buck-boost are only brought in when the input range straddles the output, because while a SEPIC will happily make 3.3 V from 12 V, nobody should be offered one for that job. An LDO survives a large drop only when the dissipation times the package’s θJA keeps the junction below its limit at your ambient, which is the real reason linear regulators lose at high current, rather than the efficiency figure itself.
The ripple ratio r is 0.3 by default, 0.4 when optimising for area and 0.25 for efficiency. The inductor is then fitted from a real catalogue series — saturation current at least 1.2× the computed peak, RMS rating above the computed RMS — and every downstream figure is recomputed with the real inductance, not the ideal one. The minimum on-time is checked at the highest input, and if the chosen frequency violates it the frequency is lowered rather than the part quietly accepted.
Output capacitance is sized three ways and the largest wins: ripple, the initial estimate for the load step, and then the closed-loop output impedance. The last one is the honest check. The loop is modelled — averaged current-mode with the sampling double pole at fsw/2, or voltage-mode with the LC double pole — a compensator is synthesised for crossover at a tenth of the switching frequency (or a fifth of the right-half-plane zero for boost and SEPIC, whichever is lower), and the peak of |Zout| times the load step is the estimated droop. If that misses the target the capacitor bank grows and the loop is redesigned, until it fits or until adding capacitance stops helping, at which point the page says so.
MLCCs are counted after DC-bias derating. A 22 µF 6.3 V 0603 at 5 V is nearer 7 µF, and a design that counts the nameplate value is the most common reason a converter rings on the bench. The derating here is a deliberately rough case-size model; the vendor’s own DC-bias curve for the exact part number is the figure to design to.
Past about 30–40 A a single phase stops being the answer, and the tool changes shape to match. A multiphase controller is paired with one smart power stage per phase, and the phase count is chosen so that each stage runs at no more than three-quarters of its rating — then one or two more phases are tried as well, because an extra phase is often cheaper than a hotter stage. Stackable converters and dual or quad power modules are paralleled the same way, and a dual module is treated as the two internal phases it really is, with its current limit checked per channel.
Interleaving is where the output capacitance is saved. With N phases shifted by 360°/N the inductor ripple currents partly cancel, and what reaches the output capacitors is a fraction of one phase’s ripple at N times the switching frequency:
which falls to nothing whenever the duty cycle is a multiple of 1/N and does little at the very low duty cycles of a 12 V to 0.8 V rail — one reason core rails are increasingly fed from 5 V or an intermediate bus. Power-stage losses are taken from each stage’s own published loss curve, fitted as a fixed plus an I² term and scaled to your input voltage and frequency. At these currents the load step, not the ripple, sizes the output bank, and it is usually polymer rather than ceramic, because polymer capacitance does not collapse under DC bias.
The board thermal setting matters more here than anywhere else. A datasheet θJA is measured on a JEDEC test board; a real high-current board with thick inner planes typically does about 30% better, and forced air better again. Pick the one that describes your board, because it decides whether a 40 A part is carrying 30 A or 20 A.
Efficiency is a loss-model estimate — conduction, switching edges, gate charge, dead time, rectifier drop, inductor DCR at temperature, and quiescent current — in forced-PWM operation. Parts with a light-load pulse-skipping or PFM mode do considerably better below about 20% load than the curve shows. Core loss is not modelled; at the ripple ratios used here it is typically a small fraction of the copper loss, but it is not zero, and on high-frequency designs it can matter.
Area is each part’s body plus a 0.25 mm courtyard, summed, plus 30% for routing and vias, single-sided. Prices are indicative 1k-quantity figures taken from a distributor or the vendor’s own store on the date recorded against each part, and they are marked where they are estimates. They move; use them to compare designs, not to quote.
Ask for a UVLO turn-on voltage and the tool sizes the EN divider against the part’s own precision-enable threshold, so the converter stays off until the input has genuinely arrived — the fix for a regulator that starts on a sagging battery and then browns out under its own inrush. Ask for a power-up delay and it sizes a capacitor on the EN node from the divider’s Thevenin resistance. An RC delay drifts with capacitor tolerance and with the input voltage, so for a sequence that has to hold across production, chain each rail’s EN from the previous one’s power-good instead — which is why power-good is a filter here, not just a nice-to-have.
Soft-start capacitance comes from CSS = tSS · ISS / Vref with the charge current from the datasheet, and the page reports the inrush current that results into the output bank — the number that decides whether an upstream eFuse or a USB host trips at power-up.
Mainland-China vendors — SG Micro, Silergy, 3PEAK, Southchip, Joulwatt and others — now make regulators that are genuinely competitive and frequently a third of the price, and many are drop-in footprint-compatible with Western parts. They are off by default for a practical reason rather than a technical one: for some products, customer, export or defence-sourcing rules exclude them, and the person running the tool is the one who knows. Tick the box and they compete on equal terms, marked CN wherever they appear. Taiwanese vendors such as Richtek are not in this group.
Every regulator, inductor series, MOSFET and diode in the survey was read from its datasheet on the date recorded against it, with a direct link to that datasheet, and the survey is kept as its own versioned file rather than buried in the page. Where a value could not be found it is recorded as missing rather than guessed, and parts with missing values carry a check mark in the shortlist. The survey is a curated set of current, recommended-for-new-design parts across the market, not an exhaustive parametric database — it will miss some excellent parts, and it will age. Tell us when it is wrong.
If the design feeds a noise-sensitive load, the PDN target impedance and decoupling impedance tools carry the same impedance argument onto the board; the buck converter calculator is the single-topology version of the arithmetic, with no part selection; and for a design that has to meet a functional-safety target, the FIT and PMHF calculator is where the regulator’s failure rate goes next.
| Date | Change |
|---|---|
| 2026-09-29 | Added high-current core-rail parts: 14 single-phase and stackable 25-100 A converters and power modules, 10 multiphase controllers (6-20 phases), 9 smart power stages with their published loss curves, 5 high-current inductor series and 10 polymer bulk capacitors. |
| 2026-09-28 | First compilation: 130 buck, boost, SEPIC, buck-boost and LDO regulators (34 from mainland-China vendors), 21 inductor series, 21 MOSFETs and 11 Schottky diodes, each read from its datasheet on the day. |
Each of these runs entirely in your browser. Nothing is uploaded, stored or sent anywhere, and none of them needs an email address.
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