← All Verification IPUSB
128b/132b
Line-coding verification for the 128b/132b block-sync scheme shared by USB4 and PCIe Gen6+ — sync-header insertion/detection and scrambling.
plannedGroup USBStandard 128b/132b line coding (USB4 / PCIe Gen6+)
Planned — scoped for this wave; deliverables not yet built. Ask if you need it sooner.
Verification IP is not safety-rated. These are testbench components — no ASIL target, no FMEDA, no IP-XACT, no safety-mechanism interface. They exist to help you verify a design, not to carry a safety argument. The safety soft-IP catalog is over here.
The deliverable
What is scoped
Scoped, not yet built
This VIP is specified against the protocol’s public standard and scheduled for the current wave. The deliverables below describe the intended shape, not shipped code.
Ask if you need it sooner
Scoping is done, so a concrete date is a conversation away. Customer demand reorders the wave.
Same shape when it lands
Every shipping VIP arrives as a clean-room bus-functional model, a passive protocol checker, and a self-checking interop testbench.
Line-coding verification for the 128b/132b block-sync scheme shared by USB4 and PCIe Gen6+ — sync-header insertion/detection and scrambling.
Key Features
- Block-sync header insertion/detection (128b payload + 4b sync header)
- Scrambler/descrambler polynomial verification
- FEC-interleave compatibility scenarios where the host protocol layers FEC on top
Standards & Compliance
128b/132b line coding (USB4 / PCIe Gen6+)
Interested in the 128b/132b VIP?
This VIP is scoped but not yet built — tell us your timeline and we will reorder the wave.
Verification IP is testbench collateral and is deliberately not safety-rated: no ASIL target, no FMEDA, and no IP-XACT descriptor. It carries no functional-safety claim.
circuit-design.space · +1-971-357-1400 · sales@circuit-design.space